static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
{
/* Select ACPI logical device, enable it and CIR Wake */
nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
/* Enable CIR Wake via PSOUT# (Pin60) */
nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
/* enable cir interrupt of mouse/keyboard IRQ event */
nvt_set_reg_bit(nvt, CIR_INTR_MOUSE_IRQ_BIT, CR_ACPI_IRQ_EVENTS);
/* enable pme interrupt of cir wakeup event */
nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
/* Select CIR Wake logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
nvt_cr_write(nvt, nvt->cir_wake_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_wake_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_cr_write(nvt, nvt->cir_wake_irq, CR_CIR_IRQ_RSRC);
nvt_dbg("CIR Wake initialized, base io port address: 0x%lx, irq: %d",
nvt->cir_wake_addr, nvt->cir_wake_irq);
}
static void nvt_cir_ldev_init(struct nvt_dev *nvt)
{
u8 val, psreg, psmask, psval;
if (is_w83667hg(nvt)) {
psreg = CR_MULTIFUNC_PIN_SEL;
psmask = MULTIFUNC_PIN_SEL_MASK;
psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
} else {
psreg = CR_OUTPUT_PIN_SEL;
psmask = OUTPUT_PIN_SEL_MASK;
psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
}
/* output pin selection: enable CIR, with WB sensor enabled */
val = nvt_cr_read(nvt, psreg);
val &= psmask;
val |= psval;
nvt_cr_write(nvt, val, psreg);
/* Select CIR logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
nvt->cir_addr, nvt->cir_irq);
}
static void nvt_cir_ldev_init(struct nvt_dev *nvt)
{
u8 val;
/* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
val &= OUTPUT_PIN_SEL_MASK;
val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
/* Select CIR logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
nvt_cr_write(nvt, nvt->cir_addr >> 8, CR_CIR_BASE_ADDR_HI);
nvt_cr_write(nvt, nvt->cir_addr & 0xff, CR_CIR_BASE_ADDR_LO);
nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
nvt->cir_addr, nvt->cir_irq);
}
/* clear config register bit without changing other bits */
static inline void nvt_clear_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
{
u8 tmp = nvt_cr_read(nvt, reg) & ~val;
nvt_cr_write(nvt, tmp, reg);
}
