/**
* omap4_pwrdm_enable_hdwr_sar - enable hardware save / restore for pwrdm
* @pwrdm: struct powerdomain * to enable HW SAR for
*
* Enables hardware save / restore for a powerdomain. This is needed by
* some power domains to properly support off mode. Currently supports
* only L3INIT powerdomain on OMAP4. Called from powerdomain core code.
* Returns 0 always.
*/
static int omap4_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm)
{
s16 inst = cpu_is_omap44xx() ? OMAP4430_CM2_L3INIT_INST :
OMAP54XX_CM_CORE_L3INIT_INST;
/*
* FIXME: This should be fixed right way by moving it into HWMOD
* or clock framework since sar control is moved to module level
*/
omap4_cminst_rmw_inst_reg_bits(OMAP4430_SAR_MODE_MASK,
1 << OMAP4430_SAR_MODE_SHIFT,
OMAP4430_CM2_PARTITION,
inst,
OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET);
omap4_cminst_rmw_inst_reg_bits(OMAP4430_SAR_MODE_MASK,
1 << OMAP4430_SAR_MODE_SHIFT,
OMAP4430_CM2_PARTITION,
inst,
OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET);
return 0;
}
u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
{
return omap4_cminst_rmw_inst_reg_bits(bits, 0x0, part, inst, idx);
}
u32 omap4_cminst_set_inst_reg_bits(u32 bits, u8 part, u16 inst, s16 idx)
{
return omap4_cminst_rmw_inst_reg_bits(bits, bits, part, inst, idx);
}
