static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { void *startup_addr = omap4_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); /* * Initialise the SCU and wake up the secondary core using * wakeup_secondary(). */ if (scu_base) scu_enable(scu_base); if (cpu_is_omap446x()) { startup_addr = omap4460_secondary_startup; pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; } /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ if (omap_secure_apis_support()) omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else __raw_writel(virt_to_phys(omap5_secondary_startup), base + OMAP_AUX_CORE_BOOT_1); }
static void __init wakeup_secondary(void) { void *startup_addr = omap_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); if (cpu_is_omap446x()) { startup_addr = omap_secondary_startup_4460; pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD; } /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ if (omap_secure_apis_support()) omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else __raw_writel(virt_to_phys(omap5_secondary_startup), base + OMAP_AUX_CORE_BOOT_1); smp_wmb(); /* * Send a 'sev' to wake the secondary core from WFE. * Drain the outstanding writes to memory */ dsb_sev(); mb(); }
static void __init wakeup_secondary(void) { static struct clockdomain *cpu1_clkdm; static void __iomem *sar_base; /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); smp_wmb(); sar_base = ioremap(OMAP44XX_SAR_RAM_BASE, SZ_16K); __raw_writel(virt_to_phys(omap_secondary_startup), sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET); if (!cpu1_clkdm) cpu1_clkdm = clkdm_lookup("mpu1_clkdm"); /* * Send a 'sev' to wake the secondary core from WFE. * Drain the outstanding writes to memory */ dsb_sev(); mb(); }
static void __init wakeup_secondary(void) { /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ omap_auxcoreboot_addr(virt_to_phys(omap_secondary_startup)); smp_wmb(); /* * Send a 'sev' to wake the secondary core from WFE. * Drain the outstanding writes to memory */ dsb_sev(); mb(); }
static void __init omap4_smp_prepare_cpus(unsigned int max_cpus) { void *startup_addr = omap4_secondary_startup; void __iomem *base = omap_get_wakeupgen_base(); /* * Initialise the SCU and wake up the secondary core using * wakeup_secondary(). */ if (scu_base) scu_enable(scu_base); if (cpu_is_omap446x()) startup_addr = omap4460_secondary_startup; /* * Write the address of secondary startup routine into the * AuxCoreBoot1 where ROM code will jump and start executing * on secondary core once out of WFE * A barrier is added to ensure that write buffer is drained */ if (omap_secure_apis_support()) omap_auxcoreboot_addr(virt_to_phys(startup_addr)); else /* * If the boot CPU is in HYP mode then start secondary * CPU in HYP mode as well. */ if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE) writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup), base + OMAP_AUX_CORE_BOOT_1); else writel_relaxed(virt_to_phys(omap5_secondary_startup), base + OMAP_AUX_CORE_BOOT_1); }