/* Read EFUSE values from control registers for OMAP3430 */
static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
struct omap_sr_data *sr_data)
{
struct omap_sr_nvalue_table *nvalue_table;
int i, j, count = 0;
sr_data->nvalue_count = 0;
sr_data->nvalue_table = NULL;
while (volt_data[count].volt_nominal)
count++;
nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
GFP_KERNEL);
if (!nvalue_table) {
pr_err("OMAP: SmartReflex: cannot allocate memory for n-value table\n");
return;
}
for (i = 0, j = 0; i < count; i++) {
u32 v;
/*
* In OMAP4 the efuse registers are 24 bit aligned.
* A readl_relaxed will fail for non-32 bit aligned address
* and hence the 8-bit read and shift.
*/
if (cpu_is_omap44xx()) {
u16 offset = volt_data[i].sr_efuse_offs;
v = omap_ctrl_readb(offset) |
omap_ctrl_readb(offset + 1) << 8 |
omap_ctrl_readb(offset + 2) << 16;
} else {
v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
}
/*
* Many OMAP SoCs don't have the eFuse values set.
* For example, pretty much all OMAP3xxx before
* ES3.something.
*
* XXX There needs to be some way for board files or
* userspace to add these in.
*/
if (v == 0)
continue;
nvalue_table[j].nvalue = v;
nvalue_table[j].efuse_offs = volt_data[i].sr_efuse_offs;
nvalue_table[j].errminlimit = volt_data[i].sr_errminlimit;
nvalue_table[j].volt_nominal = volt_data[i].volt_nominal;
j++;
}
sr_data->nvalue_table = nvalue_table;
sr_data->nvalue_count = j;
}
static void __init lvt_sr_set_nvalues(struct omap_volt_data *volt_data,
struct omap_sr_data *sr_data)
{
struct omap_sr_nvalue_table *lvt_nvalue_table;
int i, count = 0;
while (volt_data[count].volt_nominal)
count++;
lvt_nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
GFP_KERNEL);
for (i = 0; i < count; i++) {
u32 v;
/*
* In OMAP4 the efuse registers are 24 bit aligned.
* A __raw_readl will fail for non-32 bit aligned address
* and hence the 8-bit read and shift.
*/
if (cpu_is_omap44xx()) {
u16 offset = volt_data[i].lvt_sr_efuse_offs;
v = omap_ctrl_readb(offset) |
omap_ctrl_readb(offset + 1) << 8 |
omap_ctrl_readb(offset + 2) << 16;
} else {
v = omap_ctrl_readl(volt_data[i].lvt_sr_efuse_offs);
}
lvt_nvalue_table[i].efuse_offs = volt_data[i].lvt_sr_efuse_offs;
lvt_nvalue_table[i].nvalue = v;
}
sr_data->lvt_nvalue_table = lvt_nvalue_table;
sr_data->lvt_nvalue_count = count;
}
void __init_or_module omap2_cfg_debug(const struct pin_config *cfg, u8 reg)
{
u16 orig;
u8 warn = 0, debug = 0;
orig = omap_ctrl_readb(cfg->mux_reg);
#ifdef CONFIG_OMAP_MUX_DEBUG
debug = cfg->debug;
#endif
warn = (orig != reg);
if (debug || warn)
printk(KERN_WARNING
"MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
cfg->name, omap_ctrl_base_get() + cfg->mux_reg,
orig, reg);
}
/* Read EFUSE values from control registers for OMAP3430 */
static void __init sr_set_nvalues(struct omap_volt_data *volt_data,
struct omap_sr_data *sr_data)
{
struct omap_sr_nvalue_table *nvalue_table;
int i, count = 0;
while (volt_data[count].volt_nominal)
count++;
nvalue_table = kzalloc(sizeof(struct omap_sr_nvalue_table)*count,
GFP_KERNEL);
for (i = 0; i < count; i++) {
u32 v;
/*
* In OMAP4 the efuse registers are 24 bit aligned.
* A __raw_readl will fail for non-32 bit aligned address
* and hence the 8-bit read and shift.
*/
if (cpu_is_omap44xx()) {
u16 offset = volt_data[i].sr_efuse_offs;
#ifdef CONFIG_OMAP_SMARTREFLEX_CUSTOM_SENSOR
if (offset == 0) {
u32 pgain = 0, pvalue = 0, ngain = 0, nvalue = 0;
cal_reciprocal(volt_data[i].sr_nsensor, &ngain, &nvalue);
cal_reciprocal(volt_data[i].sr_psensor, &pgain, &pvalue);
v = (pgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
(ngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
(pvalue << NVALUERECIPROCAL_RNSENP_SHIFT) |
(nvalue);
} else {
v = omap_ctrl_readb(offset) |
omap_ctrl_readb(offset + 1) << 8 |
omap_ctrl_readb(offset + 2) << 16;
}
#else
v = omap_ctrl_readb(offset) |
omap_ctrl_readb(offset + 1) << 8 |
omap_ctrl_readb(offset + 2) << 16;
#endif
} else {
v = omap_ctrl_readl(volt_data[i].sr_efuse_offs);
}
nvalue_table[i].efuse_offs = volt_data[i].sr_efuse_offs;
nvalue_table[i].nvalue = v;
}
sr_data->nvalue_table = nvalue_table;
sr_data->nvalue_count = count;
}
