/* Setup free-running counter for clocksource */ static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; u32 tick_rate, tick_period; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; gpt = omap_dm_timer_request(); if (!gpt) printk(err1, clocksource_gpt.name); gpt_clocksource = gpt; omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); tick_period = (tick_rate / HZ) - 1; omap_dm_timer_set_load_start(gpt, 1, 0); clocksource_gpt.mult = clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift); if (clocksource_register(&clocksource_gpt)) printk(err2, clocksource_gpt.name); }
static void pwm_set_speed(struct omap_dm_timer *gpt, int frequency, int duty_cycle) { u32 val; u32 period; struct clk *timer_fclk; /* and you will have an overflow in 1 sec */ /* so, */ /* freq_timer -> 1s */ /* carrier_period -> 1/carrier_freq */ /* => carrier_period = freq_timer/carrier_freq */ timer_fclk = omap_dm_timer_get_fclk(gpt); period = clk_get_rate(timer_fclk) / frequency; val = 0xFFFFFFFF+1-period; omap_dm_timer_set_load(gpt, 1, val); val = 0xFFFFFFFF+1-(period*duty_cycle/256); omap_dm_timer_set_match(gpt, 1, val); /* assume overflow first: no toogle if first trig is match */ omap_dm_timer_write_counter(gpt, 0xFFFFFFFE); }
static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; gptimer = omap_dm_timer_request_specific(1); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); #else omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); #endif tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(1, &clockevent_gpt); clockevent_gpt.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_gpt); }
static int __devinit cloudsurfer_wakeup_probe(struct platform_device *pdev) { struct cloudsurfer_wakeup_struct *wkup; struct input_dev *wkup_in; u32 tick_rate, cycles; int err; /* Data structure allocation */ wkup = kzalloc(sizeof(struct cloudsurfer_wakeup_struct), GFP_KERNEL); wkup_in = input_allocate_device(); if (!wkup_in) { printk("CLOUDSURFER - Can't allocate wakeup timer input\n"); err = -ENOMEM; goto error_input_dev; } /* Timer allocation and setup */ if ( (wkup->timer=omap_dm_timer_request_specific(1)) == NULL ) { printk("CLOUDSURFER - can't allocate wakeup timer\n"); err = -ENODEV; goto error_timer; } wkup->irq = omap_dm_timer_get_irq(wkup->timer); omap_dm_timer_set_source(wkup->timer,OMAP_TIMER_SRC_32_KHZ); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(wkup->timer)); cycles = tick_rate * wakeup_seconds; omap_dm_timer_stop(wkup->timer); input_set_capability(wkup_in,EV_MSC,1); input_set_capability(wkup_in,EV_MSC,2); wkup_in->name = "cloudsurfer-wakeup"; wkup_in->phys = "cloudsurfer-wakeup/input0"; wkup_in->dev.parent = &pdev->dev; cloudsurfer_irq_data.dev_id = wkup_in; setup_irq(wkup->irq,&cloudsurfer_irq_data); input_set_drvdata(wkup_in, wkup); err = input_register_device(wkup_in); if (err) { printk("CLOUDSURFER -Can't register wakeup timer: %d\n", err); goto error_register; } omap_dm_timer_set_int_enable(wkup->timer,OMAP_TIMER_INT_OVERFLOW); omap_dm_timer_set_load_start(wkup->timer, 1, 0xffffffff - cycles); platform_set_drvdata(pdev, wkup_in); return 0; error_register: free_irq(wkup->irq, NULL); error_timer: input_free_device(wkup_in); error_input_dev: kfree(wkup); return err; }
static void omap2_gp_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { u32 period; omap_dm_timer_stop(gptimer); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; period -= 1; omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); break; case CLOCK_EVT_MODE_ONESHOT: break; case CLOCK_EVT_MODE_SHUTDOWN: omap_timer_save_context(gptimer); break; case CLOCK_EVT_MODE_RESUME: omap_timer_restore_context(gptimer); break; case CLOCK_EVT_MODE_UNUSED: break; } }
// Initialize the kernel module static int __init gptimer_test_init(void) { int ret = 0; struct clk *gt_fclk; uint32_t gt_rate; printk("gptimer test: starting moudle init\n"); // request a timer (we are asking for ANY open timer, see dmtimer.c for details on how this works) timer_ptr = omap_dm_timer_request(); if(timer_ptr == NULL){ // oops, no timers available printk("gptimer test: No more gp timers available, bailing out\n"); return -1; } // set the clock source to system clock omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); // set prescalar to 1:1 omap_dm_timer_set_prescaler(timer_ptr, 32); // figure out what IRQ our timer triggers timer_irq = omap_dm_timer_get_irq(timer_ptr); // install our IRQ handler for our timer ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "gptimer test", timer_irq_handler); if(ret){ printk("gptimer test: request_irq failed (on irq %d), bailing out\n", timer_irq); return ret; } // get clock rate in Hz gt_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(gt_fclk); // set preload, and autoreload // we set it to the clock rate in order to get 1 overflow every second omap_dm_timer_set_load(timer_ptr, 1, 0xFFFFFFFF - gt_rate); // setup timer to trigger our IRQ on the overflow event omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW); // start the timer! omap_dm_timer_start(timer_ptr); // done! printk("gptimer test: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); // return sucsess return 0; }
static int __init gptimer_request_init(void) { struct clk *gt_fclk; uint32_t gt_rate; /*Requesting for any available timer*/ timer_ptr = omap_dm_timer_request(); if (timer_ptr == NULL) { /*Timers are not available*/ printk(KERN_ERR "GPtimers are not available\n"); return -1; } switch (clock_type) { case 1: /*Set the clock source to 32Khz Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_32_KHZ source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_32_KHZ); break; case 2: /*Set the clock source to System Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_SYS_CLK source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); break; case 3: /*Set the clock source to System Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_EXT_CLK source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_EXT_CLK); break; default: printk(KERN_ERR "Invalid clock_type value. Use 1, 2 or 3\n"); return -1; } /*Figure out what IRQ our timer triggers*/ timer_irq = omap_dm_timer_get_irq(timer_ptr); /*Get clock rate in Hz*/ gt_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(gt_fclk); /*Start the timer!*/ omap_dm_timer_start(timer_ptr); printk(KERN_INFO "GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); return 0; }
static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; int src; u32* time_base = ioremap(0x4A318000, SZ_4K); inited = 1; gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); gptimer_wakeup = gptimer; #if defined(CONFIG_OMAP_32K_TIMER) src = OMAP_TIMER_SRC_32_KHZ; #else src = OMAP_TIMER_SRC_SYS_CLK; WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the " "secure 32KiHz clock source\n"); #endif if (gptimer_id != 12) WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)), "timer-gp: omap_dm_timer_set_source() failed\n"); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", gptimer_id, tick_rate); print_timer(time_base); omap2_gp_timer_irq.dev_id = (void *)gptimer; //TODO: slow for safety omap_dm_timer_set_load_start(gptimer, 1, 0); print_timer(time_base); setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(3, &clockevent_gpt); /* Timer internal resynch latency. */ clockevent_gpt.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_gpt); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); print_timer(time_base); }
static void __init omap2_gp_timer_init(void) { u32 tick_period; omap_dm_timer_init(); gptimer = omap_dm_timer_request_specific(1); BUG_ON(gptimer == NULL); omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_SYS_CLK); tick_period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / 100; tick_period -= 1; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap2_gp_timer_start(tick_period); }
static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51) { struct clk *clk_fclk; int retval, pwm_timer = lirc_rx51->pwm_timer_num; lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer); if (lirc_rx51->pwm_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n", pwm_timer); return -EBUSY; } lirc_rx51->pulse_timer = omap_dm_timer_request(); if (lirc_rx51->pulse_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n"); retval = -EBUSY; goto err1; } omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_set_source(lirc_rx51->pulse_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(lirc_rx51->pwm_timer); omap_dm_timer_enable(lirc_rx51->pulse_timer); lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer); retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler, IRQF_DISABLED | IRQF_SHARED, "lirc_pulse_timer", lirc_rx51); if (retval) { dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n"); goto err2; } clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer); lirc_rx51->fclk_khz = clk_fclk->rate / 1000; return 0; err2: omap_dm_timer_free(lirc_rx51->pulse_timer); err1: omap_dm_timer_free(lirc_rx51->pwm_timer); return retval; }
static void __init omap2_gp_clockevent_init(void) { u32 tick_rate; int src; inited = 1; gptimer = omap_dm_timer_request_specific(gptimer_id); BUG_ON(gptimer == NULL); #if defined(CONFIG_OMAP_32K_TIMER) src = OMAP_TIMER_SRC_32_KHZ; #else src = OMAP_TIMER_SRC_SYS_CLK; WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the " "secure 32KiHz clock source\n"); #endif if (gptimer_id != 12) WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)), "timer-gp: omap_dm_timer_set_source() failed\n"); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer)); if (cpu_is_omap44xx()) /* Assuming 32kHz clk is driving GPT1 */ tick_rate = 32768; /* FIXME: */ pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n", gptimer_id, tick_rate); omap2_gp_timer_irq.dev_id = (void *)gptimer; setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC, clockevent_gpt.shift); clockevent_gpt.max_delta_ns = clockevent_delta2ns(0xffffffff, &clockevent_gpt); clockevent_gpt.min_delta_ns = clockevent_delta2ns(3, &clockevent_gpt); /* Timer internal resynch latency. */ clockevent_gpt.cpumask = cpumask_of(0); clockevents_register_device(&clockevent_gpt); }
static int sholest_lvibrator_initialization(void) { unsigned long load_reg, cmp_reg; uint32_t timer_rate = 0; int ret = 0; vib_pwm_timer = omap_dm_timer_request_specific(11); if (vib_pwm_timer == NULL) ret = -ENODEV; timer_rate = clk_get_rate(omap_dm_timer_get_fclk(vib_pwm_timer)); load_reg = timer_rate * SHOLEST_LVIBRATOR_PERIOD / 1000000; cmp_reg = timer_rate * (SHOLEST_LVIBRATOR_PERIOD - SHOLEST_LVIBRATOR_DUTY) / 1000000; omap_dm_timer_set_source(vib_pwm_timer, OMAP_TIMER_SRC_32_KHZ); omap_dm_timer_set_load(vib_pwm_timer, 1, -load_reg); omap_dm_timer_set_match(vib_pwm_timer, 1, -cmp_reg); omap_dm_timer_set_pwm(vib_pwm_timer, 0, 1, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE); omap_dm_timer_write_counter(vib_pwm_timer, -2); return 0; }
static void omap2_gp_timer_set_mode(enum clock_event_mode mode, struct clock_event_device *evt) { u32 period; omap_dm_timer_stop(gptimer); switch (mode) { case CLOCK_EVT_MODE_PERIODIC: period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ; period -= 1; if (cpu_is_omap44xx()) period = 0xff; /* FIXME: */ omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period); break; case CLOCK_EVT_MODE_ONESHOT: break; case CLOCK_EVT_MODE_UNUSED: case CLOCK_EVT_MODE_SHUTDOWN: case CLOCK_EVT_MODE_RESUME: break; } }
/* Setup free-running counter for clocksource */ static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; u32 tick_rate; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; gpt = omap_dm_timer_request(); if (!gpt) printk(err1, clocksource_gpt.name); gpt_clocksource = gpt; omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); omap_dm_timer_set_load_start(gpt, 1, 0); init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate); if (clocksource_register_hz(&clocksource_gpt, tick_rate)) printk(err2, clocksource_gpt.name); }
static int __init pwm_start(void) { int ret = 0; struct clk *timer_fclk; uint32_t gt_rate; printk(KERN_INFO "Loading PWM Module... \n"); // request any timer timer_ptr = omap_dm_timer_request(); if(timer_ptr == NULL){ // no timers available printk("pwm module: No more gp timers available, bailing out\n"); return -1; } // set the clock source to the system clock ret = omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); if(ret) { printk("pwm module: could not set source\n"); return -1; } // set prescalar to 1:1 omap_dm_timer_set_prescaler(timer_ptr, 0); // figure out what IRQ our timer triggers timer_irq = omap_dm_timer_get_irq(timer_ptr); // install our IRQ handler for our timer ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "pwm", timer_irq_handler); if(ret){ printk("pwm module: request_irq failed (on irq %d), bailing out\n", timer_irq); return ret; } // get clock rate in Hz and add it to struct timer_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(timer_fclk); pwm_data_ptr.timer_rate = gt_rate; // set preload, and autoreload // we set it to a default of 1kHz set_pwm_freq(1000); // setup timer to trigger IRQ on the overflow omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW); // start the timer omap_dm_timer_start(timer_ptr); // done! printk("pwm module: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); // setup a GPIO pwm_setup_pin(38); pwm_data_ptr.pin = 38; set_pwm_dutycycle(1,150); // return success return 0; }
static int _init_gpt(void) { int irqno; int ret = 0; if ((gpt_pwm_list[IRBLASTER_PWM].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_PWM].no)) == NULL) { printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no); return -ENODEV; } omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_PWM].timer, gpt_pwm_list[IRBLASTER_PWM].source); gpt_pwm_list[IRBLASTER_PWM].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_PWM].timer)); printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_PWM].name, gpt_pwm_list[IRBLASTER_PWM].no, gpt_pwm_list[IRBLASTER_PWM].rate); if ((gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer = omap_dm_timer_request_specific(gpt_pwm_list[IRBLASTER_TIMER_CTRL].no)) == NULL) { printk(KERN_ERR "%s: failed to request dm-timer (%d)\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no); omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer); return -ENODEV; } omap_dm_timer_set_source(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, gpt_pwm_list[IRBLASTER_TIMER_CTRL].source); gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate = clk_get_rate(omap_dm_timer_get_fclk(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer)); printk(KERN_DEBUG "%s (%d) timer rate is: %d\n", gpt_pwm_list[IRBLASTER_TIMER_CTRL].name, gpt_pwm_list[IRBLASTER_TIMER_CTRL].no, gpt_pwm_list[IRBLASTER_TIMER_CTRL].rate); /* select irblaster configuration */ _select_irb_config(); /* enable timer clock */ omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); /* set modulation mod */ /* trigger on overflow and match */ omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_PWM].timer,0,1,2); omap_dm_timer_set_pwm(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, 0, 1, 2); //if ( gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config ) // omap_cfg_reg(gpt_pwm_list[IRBLASTER_TIMER_CTRL].mux_config); irqno = omap_dm_timer_get_irq(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); if (request_irq(irqno, omap2_irblaster_timer_interrupt, IRQF_DISABLED, "gp timer", NULL)) { ret = -EBUSY; goto failed_request_irq; } omap_dm_timer_set_int_enable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer, IRBLASTER_TIMER_CTRL_IT_TYPE); /* disable timer clocks after init */ omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); omap_dm_timer_disable(gpt_pwm_list[IRBLASTER_PWM].timer); init_waitqueue_head(&irb_wait); _gio_debug_init(); return 0; failed_request_irq: omap_dm_timer_free(gpt_pwm_list[IRBLASTER_PWM].timer); omap_dm_timer_free(gpt_pwm_list[IRBLASTER_TIMER_CTRL].timer); return ret; }