static int gptimer_start(void) { int err; u32 count = counter_config[0].count; BUG_ON(gptimer != NULL); /* First try to request timers from CORE power domain for OMAP3 */ if (cpu_is_omap34xx()) { gptimer = omap_dm_timer_request_specific(10); if (gptimer == NULL) gptimer = omap_dm_timer_request_specific(11); } /* Just any timer would be fine */ if (gptimer == NULL) gptimer = omap_dm_timer_request(); if (gptimer == NULL) return -ENODEV; omap_dm_timer_set_source(gptimer, OMAP_TIMER_SRC_32_KHZ); err = request_irq(omap_dm_timer_get_irq(gptimer), gptimer_interrupt, IRQF_DISABLED, "oprofile gptimer", NULL); if (err) { omap_dm_timer_free(gptimer); gptimer = NULL; printk(KERN_ERR "oprofile: unable to request gptimer IRQ\n"); return err; } if (count < 1) count = 1; omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - count); omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW); return 0; }
/* Setup free-running counter for clocksource */ static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; u32 tick_rate, tick_period; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; gpt = omap_dm_timer_request(); if (!gpt) printk(err1, clocksource_gpt.name); gpt_clocksource = gpt; omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); tick_period = (tick_rate / HZ) - 1; omap_dm_timer_set_load_start(gpt, 1, 0); clocksource_gpt.mult = clocksource_khz2mult(tick_rate/1000, clocksource_gpt.shift); if (clocksource_register(&clocksource_gpt)) printk(err2, clocksource_gpt.name); }
// Initialize the kernel module static int __init gptimer_test_init(void) { int ret = 0; struct clk *gt_fclk; uint32_t gt_rate; printk("gptimer test: starting moudle init\n"); // request a timer (we are asking for ANY open timer, see dmtimer.c for details on how this works) timer_ptr = omap_dm_timer_request(); if(timer_ptr == NULL){ // oops, no timers available printk("gptimer test: No more gp timers available, bailing out\n"); return -1; } // set the clock source to system clock omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); // set prescalar to 1:1 omap_dm_timer_set_prescaler(timer_ptr, 32); // figure out what IRQ our timer triggers timer_irq = omap_dm_timer_get_irq(timer_ptr); // install our IRQ handler for our timer ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "gptimer test", timer_irq_handler); if(ret){ printk("gptimer test: request_irq failed (on irq %d), bailing out\n", timer_irq); return ret; } // get clock rate in Hz gt_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(gt_fclk); // set preload, and autoreload // we set it to the clock rate in order to get 1 overflow every second omap_dm_timer_set_load(timer_ptr, 1, 0xFFFFFFFF - gt_rate); // setup timer to trigger our IRQ on the overflow event omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW); // start the timer! omap_dm_timer_start(timer_ptr); // done! printk("gptimer test: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); // return sucsess return 0; }
static int __init gptimer_request_init(void) { struct clk *gt_fclk; uint32_t gt_rate; /*Requesting for any available timer*/ timer_ptr = omap_dm_timer_request(); if (timer_ptr == NULL) { /*Timers are not available*/ printk(KERN_ERR "GPtimers are not available\n"); return -1; } switch (clock_type) { case 1: /*Set the clock source to 32Khz Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_32_KHZ source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_32_KHZ); break; case 2: /*Set the clock source to System Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_SYS_CLK source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); break; case 3: /*Set the clock source to System Clock*/ printk(KERN_INFO "Using OMAP_TIMER_SRC_EXT_CLK source\n"); omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_EXT_CLK); break; default: printk(KERN_ERR "Invalid clock_type value. Use 1, 2 or 3\n"); return -1; } /*Figure out what IRQ our timer triggers*/ timer_irq = omap_dm_timer_get_irq(timer_ptr); /*Get clock rate in Hz*/ gt_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(gt_fclk); /*Start the timer!*/ omap_dm_timer_start(timer_ptr); printk(KERN_INFO "GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); return 0; }
/* * Driver Initialization */ static int __init hello_init(void) { int ret; /* Request dynamic allocation of a device major number */ if (alloc_chrdev_region(&my_dev_number, 0, 1, DEVICE_NAME) < 0) { printk(KERN_DEBUG "Can't register device\n"); return -1; } /* Populate sysfs entries */ my_dev_class = class_create(THIS_MODULE, DEVICE_NAME); /* Allocate memory for the per-device structure */ hrt_devp = kmalloc(sizeof(struct HRT_dev), GFP_KERNEL); /* Allocate memory for the timer */ timer = kmalloc(sizeof(struct omap_dm_timer), GFP_KERNEL); /* Request a timer */ timer = omap_dm_timer_request(); /* Set timer source */ omap_dm_timer_set_source(timer,OMAP_TIMER_SRC_SYS_CLK); /* enable the timer */ omap_dm_timer_enable(timer); /* Request I/O region */ sprintf(hrt_devp->name, DEVICE_NAME); /* Connect the file operations with the cdev */ cdev_init(&hrt_devp->cdev, &My_fops); hrt_devp->cdev.owner = THIS_MODULE; /* Connect the major/minor number to the cdev */ ret = cdev_add(&hrt_devp->cdev, (my_dev_number), 1); if (ret) { printk("Bad cdev\n"); return ret; } /* Send uevents to udev, so it'll create /dev nodes */ device_create(my_dev_class, NULL, MKDEV(MAJOR(my_dev_number), 0), NULL, DEVICE_NAME); printk("HRT Driver Initialized.\n"); return 0; }
static int lirc_rx51_init_port(struct lirc_rx51 *lirc_rx51) { struct clk *clk_fclk; int retval, pwm_timer = lirc_rx51->pwm_timer_num; lirc_rx51->pwm_timer = omap_dm_timer_request_specific(pwm_timer); if (lirc_rx51->pwm_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting GPT%d timer\n", pwm_timer); return -EBUSY; } lirc_rx51->pulse_timer = omap_dm_timer_request(); if (lirc_rx51->pulse_timer == NULL) { dev_err(lirc_rx51->dev, ": Error requesting pulse timer\n"); retval = -EBUSY; goto err1; } omap_dm_timer_set_source(lirc_rx51->pwm_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_set_source(lirc_rx51->pulse_timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(lirc_rx51->pwm_timer); omap_dm_timer_enable(lirc_rx51->pulse_timer); lirc_rx51->irq_num = omap_dm_timer_get_irq(lirc_rx51->pulse_timer); retval = request_irq(lirc_rx51->irq_num, lirc_rx51_interrupt_handler, IRQF_DISABLED | IRQF_SHARED, "lirc_pulse_timer", lirc_rx51); if (retval) { dev_err(lirc_rx51->dev, ": Failed to request interrupt line\n"); goto err2; } clk_fclk = omap_dm_timer_get_fclk(lirc_rx51->pwm_timer); lirc_rx51->fclk_khz = clk_fclk->rate / 1000; return 0; err2: omap_dm_timer_free(lirc_rx51->pulse_timer); err1: omap_dm_timer_free(lirc_rx51->pwm_timer); return retval; }
/* * Request dmtimer * TESTED */ struct omap_dm_timer *HRTDriver_reserve_timer(void) { //Get device private data //struct HRT_dev *hrt_devp = file->private_data; struct omap_dm_timer *timer; timer = omap_dm_timer_request(); omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_SYS_CLK); omap_dm_timer_enable(timer); if (!timer) printk("\nTimer not reserved!\n"); else printk("\nTimer succesfully reserved!\n"); //setting the load enables the timer //omap_dm_timer_set_load_start(hrt_devp->gptimer, 0, 0); omap_dm_timer_start(timer); return timer; }
/* Setup free-running counter for clocksource */ static void __init omap2_gp_clocksource_init(void) { static struct omap_dm_timer *gpt; u32 tick_rate; static char err1[] __initdata = KERN_ERR "%s: failed to request dm-timer\n"; static char err2[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; gpt = omap_dm_timer_request(); if (!gpt) printk(err1, clocksource_gpt.name); gpt_clocksource = gpt; omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK); tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt)); omap_dm_timer_set_load_start(gpt, 1, 0); init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate); if (clocksource_register_hz(&clocksource_gpt, tick_rate)) printk(err2, clocksource_gpt.name); }
static int __init pwm_start(void) { int ret = 0; struct clk *timer_fclk; uint32_t gt_rate; printk(KERN_INFO "Loading PWM Module... \n"); // request any timer timer_ptr = omap_dm_timer_request(); if(timer_ptr == NULL){ // no timers available printk("pwm module: No more gp timers available, bailing out\n"); return -1; } // set the clock source to the system clock ret = omap_dm_timer_set_source(timer_ptr, OMAP_TIMER_SRC_SYS_CLK); if(ret) { printk("pwm module: could not set source\n"); return -1; } // set prescalar to 1:1 omap_dm_timer_set_prescaler(timer_ptr, 0); // figure out what IRQ our timer triggers timer_irq = omap_dm_timer_get_irq(timer_ptr); // install our IRQ handler for our timer ret = request_irq(timer_irq, timer_irq_handler, IRQF_DISABLED | IRQF_TIMER , "pwm", timer_irq_handler); if(ret){ printk("pwm module: request_irq failed (on irq %d), bailing out\n", timer_irq); return ret; } // get clock rate in Hz and add it to struct timer_fclk = omap_dm_timer_get_fclk(timer_ptr); gt_rate = clk_get_rate(timer_fclk); pwm_data_ptr.timer_rate = gt_rate; // set preload, and autoreload // we set it to a default of 1kHz set_pwm_freq(1000); // setup timer to trigger IRQ on the overflow omap_dm_timer_set_int_enable(timer_ptr, OMAP_TIMER_INT_OVERFLOW); // start the timer omap_dm_timer_start(timer_ptr); // done! printk("pwm module: GP Timer initialized and started (%lu Hz, IRQ %d)\n", (long unsigned)gt_rate, timer_irq); // setup a GPIO pwm_setup_pin(38); pwm_data_ptr.pin = 38; set_pwm_dutycycle(1,150); // return success return 0; }