static irqreturn_t omap2_irblaster_timer_interrupt_no_carrier(void)
{
int next_cycle;
struct omap_dm_timer *timer_ctrl = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].timer;
struct omap_dm_timer *timer_pwm = gpt_pwm_list[ IRBLASTER_PWM ].timer;
unsigned int timer_ctrl_period = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].period;
unsigned int timer_pwm_period = gpt_pwm_list[ IRBLASTER_PWM].period;
omap_dm_timer_write_status(timer_ctrl, OMAP_TIMER_INT_MATCH);
_gio_debug_clear();
next_cycle = *irq_irblaster_cycles;
if ( next_cycle ) {
irq_irblaster_cycles++;
gpt_set_new_cycle(timer_ctrl,timer_ctrl_period, next_cycle);
gpt_set_new_cycle(timer_pwm,timer_pwm_period, next_cycle);
}
else {
/* no trigger */
omap_dm_timer_set_pwm(timer_pwm,0,1,0);
/* stop timers */
omap_dm_timer_stop(timer_pwm);
omap_dm_timer_stop(timer_ctrl);
irb_over = 1;
wake_up_interruptible(&irb_wait);
}
_gio_debug_set();
return IRQ_HANDLED;
}
static irqreturn_t omap_rproc_watchdog_isr(int irq, void *p)
{
struct rproc *rproc = p;
struct omap_rproc_pdata *pdata = rproc->dev->platform_data;
struct omap_rproc_timers_info *timers = pdata->timers;
struct omap_dm_timer *timer = NULL;
struct omap_rproc_priv *rpp = rproc->priv;
int i;
for (i = 0; i < pdata->timers_cnt; i++) {
if (irq == omap_dm_timer_get_irq(timers[i].odt)) {
timer = timers[i].odt;
break;
}
}
if (!timer)
return IRQ_NONE;
omap_dm_timer_write_status(timer, OMAP_TIMER_INT_OVERFLOW);
if (rpp->wdt_cb)
rpp->wdt_cb(rproc);
return IRQ_HANDLED;
}
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
timer_tick();
return IRQ_HANDLED;
}
static irqreturn_t lirc_rx51_interrupt_handler(int irq, void *ptr)
{
unsigned int retval;
struct lirc_rx51 *lirc_rx51 = ptr;
retval = omap_dm_timer_read_status(lirc_rx51->pulse_timer);
if (!retval)
return IRQ_NONE;
if (retval & ~OMAP_TIMER_INT_MATCH)
dev_err_ratelimited(lirc_rx51->dev,
": Unexpected interrupt source: %x\n", retval);
omap_dm_timer_write_status(lirc_rx51->pulse_timer,
OMAP_TIMER_INT_MATCH |
OMAP_TIMER_INT_OVERFLOW |
OMAP_TIMER_INT_CAPTURE);
if (lirc_rx51->wbuf_index < 0) {
dev_err_ratelimited(lirc_rx51->dev,
": BUG wbuf_index has value of %i\n",
lirc_rx51->wbuf_index);
goto end;
}
/*
* If we happen to hit an odd latency spike, loop through the
* pulses until we catch up.
*/
do {
if (lirc_rx51->wbuf_index >= WBUF_LEN)
goto end;
if (lirc_rx51->wbuf[lirc_rx51->wbuf_index] == -1)
goto end;
if (lirc_rx51->wbuf_index % 2)
lirc_rx51_off(lirc_rx51);
else
lirc_rx51_on(lirc_rx51);
retval = pulse_timer_set_timeout(lirc_rx51,
lirc_rx51->wbuf[lirc_rx51->wbuf_index]);
lirc_rx51->wbuf_index++;
} while (retval);
return IRQ_HANDLED;
end:
/* Stop TX here */
lirc_rx51_off(lirc_rx51);
lirc_rx51->wbuf_index = -1;
omap_dm_timer_stop(lirc_rx51->pwm_timer);
omap_dm_timer_stop(lirc_rx51->pulse_timer);
omap_dm_timer_set_int_enable(lirc_rx51->pulse_timer, 0);
wake_up_interruptible(&lirc_rx51->wqueue);
return IRQ_HANDLED;
}
int finish_gptimer12 ( void )
{
omap_dm_timer_stop( battery_timer );
omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW );
omap_dm_timer_set_int_enable( battery_timer, 0 );
return 0;
}
static irqreturn_t cloudsurfer_wakeup_handler(int irq, void *_wkup_in)
{
struct input_dev *wkup_in = _wkup_in;
struct cloudsurfer_wakeup_struct *wkup = input_get_drvdata(wkup_in);
omap_dm_timer_write_status(wkup->timer, OMAP_TIMER_INT_OVERFLOW);
input_event(wkup_in,EV_MSC,1,0);
input_sync(wkup_in);
return IRQ_HANDLED;
}
static irqreturn_t omap2_irblaster_timer_interrupt_carrier(void)
{
static int toggle=0;
static int next_cycle=0;
struct omap_dm_timer *timer_ctrl = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].timer;
struct omap_dm_timer *timer_pwm = gpt_pwm_list[ IRBLASTER_PWM ].timer;
unsigned int timer_ctrl_period = gpt_pwm_list[ IRBLASTER_TIMER_CTRL].period;
const unsigned int counter_lim = 0xFFFFFFFF+1-(timer_ctrl_period/2)+1;
_gio_debug_clear();
omap_dm_timer_write_status(timer_ctrl, OMAP_TIMER_INT_MATCH);
next_cycle = *irq_irblaster_cycles;
if ( next_cycle ) {
irq_irblaster_cycles++;
gpt_set_new_cycle(timer_ctrl,timer_ctrl_period, next_cycle);
}
if (toggle) {
/* no trigger */
irq_irblaster_pwm_ctrl_reg &= ~(3<<10);
} else {
/* trigger on overflow and match */
/* output carrier */
irq_irblaster_pwm_ctrl_reg |= (2<<10);
}
toggle = (toggle+1)&0x1;
if ( !next_cycle ) {
/* stop timers */
omap_dm_timer_stop(timer_ctrl);
omap_dm_timer_stop(timer_pwm);
/* reset toogle */
toggle=0;
next_cycle=0;
irb_over = 1;
wake_up_interruptible(&irb_wait);
goto intr_end;
}
/* wait for overflow */
/* FIXME: try to find something that leaves cpu some ressources*/
while ( omap_dm_timer_read_counter(timer_ctrl) < counter_lim)
cpu_relax();
/* active/desactive pwm */
omap_dm_timer_write_reg(timer_pwm, OMAP_TIMER_CTRL_REG, irq_irblaster_pwm_ctrl_reg);
intr_end:
_gio_debug_set();
return IRQ_HANDLED;
}
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
{
struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
struct clock_event_device *evt = &clockevent_gpt;
omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
evt->event_handler(evt);
return IRQ_HANDLED;
}
static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id,
struct pt_regs *regs)
{
write_seqlock(&xtime_lock);
omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
timer_tick(regs);
write_sequnlock(&xtime_lock);
return IRQ_HANDLED;
}
/* The interrupt handler.
This is pretty basic, we only get an interrupt when the timer overflows,
We are just going to print a really obnoxious message each time
*/
static irqreturn_t timer_irq_handler(int irq, void *dev_id)
{
// keep track of how many calls we had
static int32_t irq_counter = 0;
// reset the timer interrupt status
omap_dm_timer_write_status(timer_ptr, OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_read_status(timer_ptr); // YES, you really need to do this 'wasteful' read
// print obnoxious text
printk("Meow Meow Meow %d\n", irq_counter ++);
// tell the kernel it's handled
return IRQ_HANDLED;
}
int init_gptimer12 ( void )
{
gptimer12_count = 0;
memset( &timer_manager, 0, sizeof( timer_manager ) );
battery_timer = omap_dm_timer_request_specific(12);
BUG_ON( battery_timer == NULL );
omap_dm_timer_set_source( battery_timer, OMAP_TIMER_SRC_32_KHZ );
//battery_timer_irq.dev_id = (void *)battery_timer;
//setup_irq(omap_dm_timer_get_irq(battery_timer), &battery_timer_irq);
//omap_dm_timer_set_int_enable(battery_timer, OMAP_TIMER_INT_OVERFLOW);
//omap_dm_timer_set_prescaler(battery_timer, GP_TIMER12_PRESCALAR);
omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW | OMAP_TIMER_INT_CAPTURE
| OMAP_TIMER_INT_MATCH );
omap_dm_timer_disable( battery_timer );
return 0;
}
static void timer_handler(void) {
// reset the timer interrupt status
omap_dm_timer_write_status(timer_ptr,OMAP_TIMER_INT_OVERFLOW);
omap_dm_timer_read_status(timer_ptr); //you need to do this read
//omap_dm_timer_write_counter(timer_ptr,0);
//printk("pwm module: Interrupt ");
// toggle pin
if(gpio_get_value(pwm_data_ptr.pin) == 0 ) {
gpio_set_value(pwm_data_ptr.pin,1);
//printk("high \n");
}
else {
gpio_set_value(pwm_data_ptr.pin,0);
//printk("low \n");
}
}
int request_gptimer12( struct gptimer12_timer *timer )
{
int loop_count;
int empty_slot = -1;
unsigned int next_time = 0;
unsigned int current_time = 0;
//unsigned int temp;
unsigned char update_flag = 0;
// printk("request_gptimer12 called \n");
if ( gptimer12_count >= MAX_GPTIMER12_INSTANCE )
{
printk( "Error... max gptimer12 instance" );
return -1;
}
//CM_ICLKEN_WKUP |= 1 << 1;
cm_val = cm_read_mod_reg( WKUP_MOD, CM_ICLKEN1 );
cm_val = cm_val | ( 1 << 1 );
cm_write_mod_reg( cm_val, WKUP_MOD, CM_ICLKEN1 );
//modify exist entry
for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL )
{
if( strcmp( timer_manager[loop_count].timer.name, timer->name ) == 0 )
{
//printk("timer update \n");
memcpy( &( timer_manager[loop_count].timer ), timer, sizeof( struct gptimer12_timer ) );
timer_manager[loop_count].remain_time = timer->expire_time;
update_flag = 1;
}
}
}
next_time = timer->expire_time;
if ( update_flag == 0 )
{
//add new entry
for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ )
{
if ( ( timer_manager[loop_count].timer.name ) == NULL )
{
empty_slot = loop_count;
break;
}
}
//printk("empty_slot : %d, loop_count : %d\n",empty_slot,loop_count);
if ( empty_slot == -1 )
{
printk("Error.. No empty slot ");
return -1;
}
gptimer12_count++;
memcpy(&(timer_manager[empty_slot].timer),timer, sizeof(struct gptimer12_timer));
timer_manager[empty_slot].remain_time = timer->expire_time;
// printk("test3 : gptimer12_count : %d\n",gptimer12_count);
if ( gptimer12_count == 1 )
{
omap_dm_timer_enable( battery_timer );
prcm_wakeup_event_control( PRCM_GPT12, PRCM_ENABLE );
omap_dm_timer_write_status( battery_timer, OMAP_TIMER_INT_OVERFLOW );
omap_dm_timer_set_int_enable( battery_timer, OMAP_TIMER_INT_OVERFLOW );
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL )
timer_manager[loop_count].remain_time -= next_time;
}
omap_dm_timer_set_load_start( battery_timer, 0, 0xffffffff - GP_TIMER12_SEC_TO_TICK(next_time) );
//CM_ICLKEN_WKUP &= ~(1 << 1);
#if 0
cm_val = cm_read_mod_reg(WKUP_MOD,CM_ICLKEN1);
cm_val = cm_val&~(1<<1);
cm_write_mod_reg(cm_val,WKUP_MOD,CM_ICLKEN1);
#endif
timer->active = true;
return 1;
}
}
omap_dm_timer_stop( battery_timer ); //:commented this
#if 1
current_time = GP_TIMER12_TICK_TO_SEC( 0xffffffff - omap_dm_timer_read_counter(battery_timer) );
#endif
for ( loop_count = 0; loop_count < MAX_GPTIMER12_INSTANCE; loop_count++ )
{
timer_manager[loop_count].remain_time += current_time;
#if 0
if((timer_manager[loop_count].timer.name) != 0)
{
if((timer_manager[loop_count].remain_time) == 0)
timer_manager[loop_count].remain_time = current_time;
}
#endif
}
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL )
{
next_time = timer_manager[loop_count].remain_time;
break;
}
}
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL )
{
if ( next_time > timer_manager[loop_count].remain_time )
next_time = timer_manager[loop_count].remain_time;
}
}
for ( loop_count = 0 ; loop_count < MAX_GPTIMER12_INSTANCE ; loop_count++ )
{
if ( timer_manager[loop_count].timer.name != NULL )
timer_manager[loop_count].remain_time -= next_time;
}
// timer
prcm_wakeup_event_control( PRCM_GPT12, PRCM_ENABLE );
omap_dm_timer_set_int_enable( battery_timer, OMAP_TIMER_INT_OVERFLOW );
omap_dm_timer_set_load_start( battery_timer, 0, 0xffffffff - GP_TIMER12_SEC_TO_TICK(next_time) );
//CM_ICLKEN_WKUP &= ~(1 << 1);
#if 0
cm_val = cm_read_mod_reg(WKUP_MOD,CM_ICLKEN1);
cm_val = cm_val&~(1<<1);
cm_write_mod_reg(cm_val,WKUP_MOD,CM_ICLKEN1);
// printk("requested gptimer12_count : %d \n",gptimer12_count);
#endif
timer->active = true;
return 1;
}
static irqreturn_t gptimer_interrupt(int irq, void *arg)
{
omap_dm_timer_write_status(gptimer, OMAP_TIMER_INT_OVERFLOW);
oprofile_add_sample(get_irq_regs(), 0);
return IRQ_HANDLED;
}