/** * omap2_dm_timer_init - top level regular device initialization * * Uses dedicated hwmod api to parse through hwmod database for * given class name and then build and register the timer device. */ static int __init omap2_dm_timer_init(void) { int ret; /* If dtb is there, the devices will be created dynamically */ if (of_have_populated_dt()) return -ENODEV; ret = omap_hwmod_for_each_by_class("timer", omap_timer_init, NULL); if (unlikely(ret)) { pr_err("%s: device registration failed.\n", __func__); return -EINVAL; } return 0; }
static int __init omap2_system_dma_init(void) { struct platform_device *pdev; int res; res = omap_hwmod_for_each_by_class("dma", omap2_system_dma_init_dev, NULL); if (res) return res; if (of_have_populated_dt()) return res; pdev = platform_device_register_full(&omap_dma_dev_info); if (IS_ERR(pdev)) return PTR_ERR(pdev); return res; }
static void omap_init_mcspi(void) { omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL); }
int __init omap_hsi_dev_init(void) { /* Keep this for genericity, although there is only one hwmod for HSI */ return omap_hwmod_for_each_by_class(OMAP_HSI_HWMOD_CLASSNAME, omap_hsi_register, NULL); }
int __init omap_devinit_smartreflex(void) { return omap_hwmod_for_each_by_class("smartreflex", sr_dev_init, NULL); }
void __init omap2_init_common_infrastructure(void) { u8 postsetup_state; if (cpu_is_omap242x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2420_hwmod_init(); } else if (cpu_is_omap243x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2430_hwmod_init(); } else if (cpu_is_omap34xx()) { omap3xxx_powerdomains_init(); omap2_clockdomains_init(); omap3xxx_hwmod_init(); } else if (cpu_is_ti81xx()) { ti81xx_powerdomains_init(); omap2_clockdomains_init(); ti81xx_hwmod_init(); } else if (cpu_is_omap44xx()) { omap44xx_powerdomains_init(); omap44xx_clockdomains_init(); omap44xx_hwmod_init(); } else { pr_err("Could not init hwmod data - unknown SoC\n"); } /* Set the default postsetup state for all hwmods */ #ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_IDLE; #else postsetup_state = _HWMOD_STATE_ENABLED; #endif omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); /* * Set the default postsetup state for unusual modules (like * MPU WDT). * * The postsetup_state is not actually used until * omap_hwmod_late_init(), so boards that desire full watchdog * coverage of kernel initialization can reprogram the * postsetup_state between the calls to * omap2_init_common_infra() and omap2_init_common_devices(). * * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional */ postsetup_state = _HWMOD_STATE_DISABLED; omap_hwmod_for_each_by_class("wd_timer", _set_hwmod_postsetup_state, &postsetup_state); omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_ti816x()) ti816x_clk_init(); else if (cpu_is_ti814x()) ti814x_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown SoC\n"); }
static void omap_init_elm(void) { omap_hwmod_for_each_by_class("elm", omap_elm_init, NULL); }
/* * gpio_init needs to be done before * machine_init functions access gpio APIs. * Hence gpio_init is a postcore_initcall. */ static int __init omap2_gpio_init(void) { return omap_hwmod_for_each_by_class("gpio", omap2_gpio_dev_init, NULL); }
static int __init omap2_system_dma_init(void) { return omap_hwmod_for_each_by_class("dma", omap2_system_dma_init_dev, NULL); }