void __init dove_init_irq(void) { int i; orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); /* * Initialize gpiolib for GPIOs 0-71. */ orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START, gpio0_irqs); orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32, gpio1_irqs); orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); /* * Mask and clear PMU interrupts */ writel(0, PMU_INTERRUPT_MASK); writel(0, PMU_INTERRUPT_CAUSE); for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); set_irq_flags(i, IRQF_VALID); } irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); }
void __init dove_init_irq(void) { int i; orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START); irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32); irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64); writel(0, PMU_INTERRUPT_MASK); writel(0, PMU_INTERRUPT_CAUSE); for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq); irq_set_status_flags(i, IRQ_LEVEL); set_irq_flags(i, IRQF_VALID); } irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); }
void __init kirkwood_init_irq(void) { int i; orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); /* * Mask and clear GPIO IRQ interrupts. */ writel(0, GPIO_LEVEL_MASK(0)); writel(0, GPIO_EDGE_MASK(0)); writel(0, GPIO_EDGE_CAUSE(0)); writel(0, GPIO_LEVEL_MASK(32)); writel(0, GPIO_EDGE_MASK(32)); writel(0, GPIO_EDGE_CAUSE(32)); for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) { set_irq_chip(i, &orion_gpio_irq_chip); set_irq_handler(i, handle_level_irq); irq_desc[i].status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); }
void __init kirkwood_init_irq(void) { orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); /* * Initialize gpiolib for GPIOs 0-49. */ orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START, gpio0_irqs); orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs); }
void __init mv78xx0_init_irq(void) { orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); orion_gpio_init(0, 32, GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START); irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); }
void __init mv78xx0_init_irq(void) { orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF)); /* * Initialize gpiolib for GPIOs 0-31. (The GPIO interrupt mask * registers for core #1 are at an offset of 0x18 from those of * core #0.) */ orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, mv78xx0_core_index() ? 0x18 : 0, IRQ_MV78XX0_GPIO_START, gpio0_irqs); }
void __init orion5x_init_irq(void) { orion_irq_init(0, MAIN_IRQ_MASK); /* * Initialize gpiolib for GPIOs 0-31. */ orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); }
void __init dove_init_irq(void) { orion_irq_init(1, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF); orion_irq_init(33, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF); set_handle_irq(dove_legacy_handle_irq); /* * Initialize gpiolib for GPIOs 0-71. */ orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, IRQ_DOVE_GPIO_START, gpio0_irqs); orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 32, gpio1_irqs); orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0, IRQ_DOVE_GPIO_START + 64, gpio2_irqs); }
void __init dove_init_irq(void) { int i; orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); /* * Mask and clear GPIO IRQ interrupts. */ writel(0, GPIO_LEVEL_MASK(0)); writel(0, GPIO_EDGE_MASK(0)); writel(0, GPIO_EDGE_CAUSE(0)); /* * Mask and clear PMU interrupts */ writel(0, PMU_INTERRUPT_MASK); writel(0, PMU_INTERRUPT_CAUSE); for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) { set_irq_chip(i, &orion_gpio_irq_chip); set_irq_handler(i, handle_level_irq); irq_desc[i].status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { set_irq_chip(i, &pmu_irq_chip); set_irq_handler(i, handle_level_irq); irq_desc[i].status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); }
void __init kirkwood_init_irq(void) { orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); /* */ orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, IRQ_KIRKWOOD_GPIO_START + 32); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); }
void __init orion5x_init_irq(void) { orion_irq_init(1, MAIN_IRQ_MASK); #ifdef CONFIG_MULTI_IRQ_HANDLER set_handle_irq(orion5x_legacy_handle_irq); #endif /* * Initialize gpiolib for GPIOs 0-31. */ orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START, gpio0_irqs); }
static int __init orion_add_irq_domain(struct device_node *np, struct device_node *interrupt_parent) { int i = 0, irq_gpio; void __iomem *base; do { base = of_iomap(np, i); if (base) { orion_irq_init(i * 32, base); i++; } } while (base); irq_domain_add_legacy(np, i * 32, 0, 0, &irq_domain_simple_ops, NULL); irq_gpio = i * 32; orion_gpio_of_init(irq_gpio); return 0; }
void __init mv78xx0_init_irq(void) { orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); }
void __init loki_init_irq(void) { orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF)); }