static void gyca_mutex_unlock(void) { if(gyca_email_mutex != OSAL_INVALID_ID) osal_mutex_unlock(gyca_email_mutex); else return ; }
int ali_ftl_sync() //for TDS { struct ali_ftl_info *afi = aliFTLDevice; struct unfinish_job *ujob = NULL; int i, ret, isErr; isErr = 0; for(i = 0; i < afi->sectionPerPartition; i++) { osal_mutex_lock(afi->ali_ftl_mutex,OSAL_WAIT_FOREVER_TIME); //for TDS while(!list_empty(&afi->secInfo[i].ujob_busy)){ ujob=list_entry(afi->secInfo[i].ujob_busy.next,struct unfinish_job, ulist); ret = finish_job(afi, ujob); if(ret){ ALI_FTL_ERR("[WARN] %s: secIdx %d, ujob 0x%x sync fail...\n", __FUNCTION__, i, ujob); isErr = 1; } } osal_mutex_unlock(afi->ali_ftl_mutex); //for TDS } return (isErr)? -1 : 0; }
//------------- USBH control transfer -------------// bool usbh_control_xfer (uint8_t dev_addr, tusb_control_request_t* request, uint8_t* data) { usbh_device_t* dev = &_usbh_devices[dev_addr]; const uint8_t rhport = dev->rhport; TU_ASSERT(osal_mutex_lock(dev->control.mutex_hdl, OSAL_TIMEOUT_NORMAL)); dev->control.request = *request; dev->control.pipe_status = 0; // Setup Stage hcd_setup_send(rhport, dev_addr, (uint8_t*) &dev->control.request); TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL)); // Data stage : first data toggle is always 1 if ( request->wLength ) { hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), data, request->wLength); TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL)); } // Status : data toggle is always 1 hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0); TU_VERIFY(osal_semaphore_wait(dev->control.sem_hdl, OSAL_TIMEOUT_NORMAL)); osal_mutex_unlock(dev->control.mutex_hdl); if ( XFER_RESULT_STALLED == dev->control.pipe_status ) return false; if ( XFER_RESULT_FAILED == dev->control.pipe_status ) return false; return true; }
void tr_condWait( tr_cond_t * c, tr_lock_t * l ) { UINT32 fptn; osal_mutex_unlock(*l); osal_flag_wait(&fptn, g_trans_flag, *c, OSAL_TWF_ANDW| OSAL_TWF_CLR, OSAL_WAIT_FOREVER_TIME); osal_mutex_lock(*l, OSAL_WAIT_FOREVER_TIME); }
//joey, 20120503, for idle reset proc service. INT32 nim_s3821_idle_reset_proc(struct nim_device *dev) { UINT8 data = 0; //joey, 20120504, add for only act as C3811 needs. nim_s3821_read(dev, 0x3b, &data, 1); if (MAGIC_CONST_1 == data) // check if S3811/C3811. { nim_s3821_read(dev, 0x147, &data, 1); if (data > MAGIC_CONST_0) // denote for C3811. { //joey, 20120613, for register access protection when HW operation. struct nim_s3821_private *dev_priv = (struct nim_s3821_private *)(dev->priv); UINT32 tmp_data = 0; osal_mutex_lock(dev_priv->nim_s3821_i2c_mutex, OSAL_WAIT_FOREVER_TIME); //libc_printf("----------------80/40 whole chip reset!\n"); //step 1: do the COFDM whole reset. tmp_data = *(volatile UINT32 *)0xb8000084; osal_delay(10); tmp_data = tmp_data | (1 << 22); *(volatile UINT32 *)0xb8000084 = tmp_data; osal_delay(10); tmp_data = tmp_data & (~(1 << 22)); *(volatile UINT32 *)0xb8000084 = tmp_data; osal_delay(10); //joey, 20120613, for register access protection when HW operation. osal_mutex_unlock(dev_priv->nim_s3821_i2c_mutex); // step 2: store in the init register values. nim_s3821_init_config(dev); } } return SUCCESS; }
static UINT32 jpeg_process(void *value) { unsigned long process = *(unsigned long*)value; unsigned long err = process >> 24; process = (process * 100) >> 16; if(process > 100) process = 100; osal_mutex_lock(jpeg_file.lock, TMO_FEVR); if(jpeg_file.mp_cb) { if(err == 0) jpeg_file.mp_cb(MP_IMAGE_DECODE_PROCESS, process); else jpeg_file.mp_cb(MP_IMAGE_DECODER_ERROR, err); } osal_mutex_unlock(jpeg_file.lock); return 0; }
//joey, 20120503, for unlock interrupt proc service. //joey, 20120614, for add-in tf exp interrupt proc service. static INT32 nim_s3821_unlock_int_proc(struct nim_device *dev) { UINT8 data = 0; // step A. read out interrupt information. nim_s3821_read(dev, 0x02, &data, 1); // Step B. check if unlock or tf buffer exception. if ((0x40 == (data & 0x40)) || (0x20 == (data & 0x20))) { //libc_printf("----------------unlock interrupt whole chip reset!\n"); //find the interrupt struct nim_s3821_private *dev_priv = (struct nim_s3821_private *)(dev->priv); UINT32 tmp_data = 0; //joey, 20120613, for register access protection when HW operation. osal_mutex_lock(dev_priv->nim_s3821_i2c_mutex, OSAL_WAIT_FOREVER_TIME); //step 1: do the COFDM whole reset. tmp_data = *(volatile UINT32 *)0xb8000084; osal_delay(10); tmp_data = tmp_data | (1 << 22); *(volatile UINT32 *)0xb8000084 = tmp_data; osal_delay(10); tmp_data = tmp_data & (~(1 << 22)); *(volatile UINT32 *)0xb8000084 = tmp_data; osal_delay(10); //joey, 20120613, for register access protection when HW operation. osal_mutex_unlock(dev_priv->nim_s3821_i2c_mutex); // step 2: store in the init register values. nim_s3821_init_config(dev); //set back the channel bw. //bandwidth setting. nim_s3821_read(dev, 0x13, &data, 1); data &= 0xcf; // clear the bit[5:4], chan_bw switch(dev_priv->s3821_cur_channel_info.channel_bw) { case BW_6M: data |= (S3821_BW_6M << 4); break; case BW_7M: data |= (S3821_BW_7M << 4); break; case BW_8M: data |= (S3821_BW_8M << 4); break; default: data |= (S3821_BW_8M << 4); if(dev_priv->log_en) { NIM_S3821_DEBUG("Error! UnKnown bandwidth mode\n"); } break; } nim_s3821_write(dev, 0x13, &data, 1); // step 3: 80/40 the COFDM. data = 0x80; nim_s3821_write(dev, 0x00, &data, 1); data = 0x40; nim_s3821_write(dev, 0x00, &data, 1); NIM_S3821_DEBUG("Finish TF exception interrupt process!\n"); } return SUCCESS; }