static int jz_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
unsigned long flags;
spin_lock_irqsave(&timer_lock,flags);
ost_writel(OSTCNTL, 0);
ost_writel(OSTCNTH, 0);
ost_writel(OSTDR, evt - 1);
tcu_writel(TCU_TMCR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TESR, (1 << OST_TIMER_BIT));
spin_unlock_irqrestore(&timer_lock,flags);
// printk("1 jz_set_next_event = %ld\n",evt);
return 0;
}
void __cpuinit jz_clocksource_init(void)
{
struct clk *ext_clk = clk_get(NULL,"ext1");
ost_writel(OST_CNTL, 0);
ost_writel(OST_CNTH, 0);
ost_writel(OST_DR, 0);
ost_writel(OST_TFCR, TFR_OSTF);
ost_writel(OST_TMSR, TMR_OSTM);
ost_writel(OST_TSCR, TSR_OSTS);
ost_writel(OST_CSR, OSTCSR_CNT_MD);
ost_writel(OST_TCSR, CSRDIV(CLKSOURCE_DIV));
ost_writel(OST_TESR, OST_EN);
clocksource_jz.mult =
clocksource_hz2mult(clk_get_rate(ext_clk) / CLKSOURCE_DIV, clocksource_jz.shift);
clk_put(ext_clk);
clocksource_register(&clocksource_jz);
}
void jz_cpu1_clockevent_init(void)
{
unsigned int latch = (SYS_TIMER_CLK + (HZ >> 1)) / HZ;
int ret;
unsigned int cpu = smp_processor_id();
struct clock_event_device *cd = &jz_clockevent_device;
tcu_writel(TCU_TECR, (1 << OST_TIMER_BIT));
ret = request_irq(IRQ_TCU0, jz_cpu1timer_interrupt,
IRQF_DISABLED | IRQF_PERCPU | IRQF_TIMER,
"jz-timerirq",
&jz_clockevent_device);
if (ret < 0) {
pr_err("timer request irq error\n");
BUG();
}
tcu_writel(TCU_TMSR, (1 << OST_TIMER_BIT));
ost_writel(OSTCSR, CSR_DIV16 | CSR_EXT_EN);
ost_writel(OSTCNTL, 0);
ost_writel(OSTCNTH, 0);
ost_writel(OSTDR, latch - 1);
/*
cd->mult =
clocksource_hz2mult(SYS_TIMER_CLK, cd->shift);
cd->min_delta_ticks = 1;
cd->max_delta_ticks = 0xfffe;
cd->cpumask = cpumask_of(cpu);
clockevents_register_device(cd);
*/
cd->cpumask = cpumask_of(cpu);
clockevents_config_and_register(cd,SYS_TIMER_CLK,4,65530);
}
static void jz_set_mode(enum clock_event_mode mode,
struct clock_event_device *evt)
{
unsigned long flags;
unsigned int latch = (SYS_TIMER_CLK + (HZ >> 1)) / HZ;
// printk("%s %d mode = %d\n",__FILE__,__LINE__,mode);
spin_lock_irqsave(&timer_lock,flags);
curmode = mode;
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
ost_writel(OSTCNTL, 0);
ost_writel(OSTCNTH, 0);
ost_writel(OSTDR, latch - 1);
tcu_writel(TCU_TFCR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TMCR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TESR, (1 << OST_TIMER_BIT));
break;
case CLOCK_EVT_MODE_ONESHOT:
break;
case CLOCK_EVT_MODE_UNUSED:
case CLOCK_EVT_MODE_SHUTDOWN:
tcu_writel(TCU_TECR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TMSR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TFCR, (1 << OST_TIMER_BIT));
break;
case CLOCK_EVT_MODE_RESUME:
tcu_writel(TCU_TFCR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TMCR, (1 << OST_TIMER_BIT));
tcu_writel(TCU_TESR, (1 << OST_TIMER_BIT));
break;
}
spin_unlock_irqrestore(&timer_lock,flags);
}
