// Writes a 32-bit value to a PCI device's configuration space.
void pci_config_write_dword(uint32_t bus, uint32_t device, uint32_t function, uint32_t offset, uint32_t data) {
uint32_t t_bus = bus & 0xFF;
uint32_t t_device = device & 0x1F;
uint32_t t_function = function & 0x07;
uint32_t t_offset = offset & 0xFC;
uint32_t address = PCI_IO_ENABLE | (t_bus << 16) | (t_device << 11) | (t_function << 8) | t_offset;
outd(PCI_IO_CONFIG_ADDRESS, address);
outd(PCI_IO_CONFIG_DATA, data);
}
u32 pciConfigReadDword(u8 bus, u8 slot, u8 func, u8 offset)
{
u32 address = ((u32)bus << 16) | ((u32)slot << 11) | ((u32)func << 8) |
(offset & 0xFC) | ((u32)0x80000000);
outd(pciConfigAddressPort, (u32)address);
return (u32)ind(pciConfigDataPort);
}
u16 pciConfigReadWord(u8 bus, u8 slot, u8 func, u8 offset)
{
u32 address = ((u32)bus << 16) | ((u32)slot << 11) | ((u32)func << 8) |
(offset & 0xFC) | ((u32)0x80000000);
outd(pciConfigAddressPort, address);
return (u16)((ind(pciConfigDataPort) >> ((offset & 2) << 3)) & 0xFFFF);
}
// Reads a 32-bit value from a PCI device's configuration space.
uint32_t pci_config_read_dword(uint32_t bus, uint32_t device, uint32_t function, uint32_t offset) {
uint32_t t_bus = bus & 0xFF;
uint32_t t_device = device & 0x1F;
uint32_t t_function = function & 0x07;
uint32_t t_offset = offset & 0xFC;
uint32_t address = PCI_IO_ENABLE | (t_bus << 16) | (t_device << 11) | (t_function << 8) | t_offset;
outd(PCI_IO_CONFIG_ADDRESS, address);
return ind(PCI_IO_CONFIG_DATA);
}
static void _pci_read(uint32_t bus, uint32_t slot, uint32_t func, struct pci_header *hdr) {
uint32_t addr;
uint32_t i;
uint32_t *hdr_data = (void*) hdr;
addr = (bus << 16) | (slot << 11) | (func << 8) | 0x80000000;
for (i = 0; i < 15; i++) {
outd(0xCF8, addr | (i << 2));
hdr_data[i] = ind(0xCFC);
}
}
static int __write32(struct bus_device *inst, addr_t addr, uint64_t val)
{
struct bus_device *bus = inst->bus;
bus_write_fp bus_write32;
if (bus) {
bus_write32 = bus->get_write_fp(bus, widthof(uint32_t));
return bus_write32(bus, inst->base + addr, val);
} else {
outd((uint32_t)addr, val);
return 0;
}
}
BattleLogsPlugin::~BattleLogsPlugin()
{
//if (started) {
QString date = QDate::currentDate().toString("yyyy-MM-dd");
QString time = QTime::currentTime().toString("hh'h'mm'm'ss's'");
QString id0 = QString::number(id1);
QString id1 = QString::number(id2);
QDir d("");
if(!d.exists("logs/battles/" + date)) {
d.mkpath("logs/battles/" + date);
}
if (raw) {
QFile out;
out.setFileName(QString("logs/battles/%1/%2-%3-%4.poreplay").arg(date, time, id0, id1));
out.open(QIODevice::WriteOnly);
out.write("battle_logs_v3\n");
/* Writing configuration */
DataStream outd(&out);
conf.teams[0] = &team1;
conf.teams[1] = &team2;
outd << conf;
out.write(toSend);
out.close();
}
if (text) {
QFile out;
out.setFileName(QString("logs/battles/%1/%2-%3-%4.html").arg(date, time, id0, id1));
out.open(QIODevice::WriteOnly);
out.write(log->getLog().join("").toUtf8());
out.close();
}
//}
if (input) {
input->deleteTree();
}
delete input, input = NULL;
}
NetworkInterfaceController *rtlInstall(PciConfigHeaderBasic *pci)
{
u32 interrupt = pci->interruptLine;
NetworkInterfaceController *nic = getNetworkInterfaceController(interrupt);
nic->interrupt = interrupt;
u16 base = pci->baseAddr[0] & ~0b11;
nic->baseAddress = base;
// Bring the chip out of low-power mode
int config1 = ind(base + Config1);
// Put the chip into low-power mode
outd(base + Cfg9346, 0xC0);
irqInstallHandler(interrupt, handler);
return nic;
}
/* vfprint - formatted output to f or string bp */
void vfprint(FILE *f, char *bp, const char *fmt, va_list ap) {
for (; *fmt; fmt++)
if (*fmt == '%')
switch (*++fmt) {
case 'd': bp = outd(va_arg(ap, int), f, bp); break;
case 'D': bp = outd(va_arg(ap, long), f, bp); break;
case 'U': bp = outu(va_arg(ap, unsigned long), 10, f, bp); break;
case 'u': bp = outu(va_arg(ap, unsigned), 10, f, bp); break;
case 'o': bp = outu(va_arg(ap, unsigned), 8, f, bp); break;
case 'X': bp = outu(va_arg(ap, unsigned long), 16, f, bp); break;
case 'x': bp = outu(va_arg(ap, unsigned), 16, f, bp); break;
case 'f': case 'e':
case 'g': {
static char format[] = "%f";
char buf[128];
format[1] = *fmt;
sprintf(buf, format, va_arg(ap, double));
bp = outs(buf, f, bp);
}
; break;
case 's': bp = outs(va_arg(ap, char *), f, bp); break;
case 'p': {
void *p = va_arg(ap, void *);
if (p)
bp = outs("0x", f, bp);
bp = outu((unsigned long)p, 16, f, bp);
break;
}
case 'c': if (f) fputc(va_arg(ap, int), f); else *bp++ = va_arg(ap, int); break;
case 'S': { char *s = va_arg(ap, char *);
int n = va_arg(ap, int);
if (s)
for ( ; n-- > 0; s++)
if (f) (void)putc(*s, f); else *bp++ = *s;
} break;
case 'k': { int t = va_arg(ap, int);
static char *tokens[] = {
#define xx(a,b,c,d,e,f,g) g,
#define yy(a,b,c,d,e,f,g) g,
#include "token.h"
};
assert(tokens[t&0177]);
bp = outs(tokens[t&0177], f, bp);
} break;
case 't': { Type ty = va_arg(ap, Type);
assert(f);
outtype(ty ? ty : voidtype, f);
} break;
case 'w': { Coordinate *p = va_arg(ap, Coordinate *);
if (p->file && *p->file) {
bp = outs(p->file, f, bp);
bp = outs(":", f, bp);
}
bp = outd(p->y, f, bp);
} break;
case 'I': { int n = va_arg(ap, int);
while (--n >= 0)
if (f) (void)putc(' ', f); else *bp++ = ' ';
} break;
default: if (f) (void)putc(*fmt, f); else *bp++ = *fmt; break;
}
else if (f)
// Start the hardware at open or resume
void rtlStart(NetworkInterfaceController *nic)
{
u16 base = nic->baseAddress;
/* Send 0x00 to the CONFIG_1 register (0x52) to set the LWAKE + LWPTN to
* active high. this should essentially *power on* the device. */
outd(base + Cfg9346, 0x00);
outb(base + Config1, 0x00);
/* Next, we should do a software reset to clear the RX and TX buffers and
* set everything back to defaults. Do this to eliminate the possibility of
* there still being garbage left in the buffers or registers on power on.
* Sending 0x10 to the Command register (0x37) will send the RTL8139 into a
* software reset. Once that byte is sent, the RST bit must be checked to
* make sure that the chip has finished the reset. If the RST bit is high,
* then the reset is still in operation.
* There is a minor bug in Qemu. If you check the command register before
* performing a soft reset, you may find the RST bit is high (1). Just
* ignore it and carry on with the initialisation procedure. */
outb(base + ChipCmd, CmdReset);
// Check that the chip has finished the reset
while (true)
{
/// todo: impose a timer in this loop
if ((ind(base + ChipCmd) & CmdReset) == 0) break;
}
/// set MAC address here?
//outd(base + Cfg9346, 0xC0);
//outd(base + MAC0 + 0, *(unsigned long *)(tp->hwaddr.addr + 0));
//outd(base + MAC0 + 4, *(unsigned long *)(tp->hwaddr.addr + 4));
/* For this part, we will send the chip a memory location to use as its
* receive buffer start location. One way to do it, would be to define a
* buffer variable and send that variables memory location to the RBSTART
* register (0x30). */
char rx_buffer[8192 + 16 + 1500];
outd(base + RxBuf, (u32)rx_buffer); // RBSTART
/* We want to put this in loopback mode, which means anything transmitted
* is immediately received. Also set burst size. */
outd(base + TxConfig, (txDmaBurst << 8) | txLoopback);
/* Before hoping to see a packet coming to you, you should tell the RTL8139
* to accept packets based on various rules. The configuration register is RCR. */
outd(base + RxConfig, 0xF | (1 << 7));
/* Enable RX and TX */
outb(base + ChipCmd, CmdRxEnb | CmdTxEnb);
outd(base + RxMissed, 0);
/* The Interrupt Mask Register (IMR) and Interrupt Service Register (ISR)
* are responsible for firing up different IRQs. The IMR bits line up with
* the ISR bits to work in sync. If an IMR bit is low, then the
* corresponding ISR bit with never fire an IRQ when the time comes for it
* to happen. The IMR is located at 0x3C and the ISR is located at 0x3E. */
// Enable interrupts by setting the interrupt mask. These will now fire an IRQ
outw(base + IntrMask, 0x0005);
printf("RTL8139 INITIALIZED\n");
}
