static READ_HANDLER( bankedram_r ) { if (videobank & 0x01) { if (videobank & 0x04) return paletteram_r(offset + 0x0800); else return paletteram_r(offset); } else return ram[offset]; }
static READ_HANDLER( bankedram_r ) { if (palette_selected) return paletteram_r(offset); else return ram[offset]; }
static READ_HANDLER( wardner_ram_rom_r ) { int wardner_data = 0; if (wardner_membank == 0) { int wardner_bank = offset + 0x8000; offset &= 0xfff; switch (wardner_bank & 0xe000) { case 0x8000: wardner_data = wardner_sprite_r(offset); break; case 0xa000: if (offset < 0xe00) { wardner_data = paletteram_r(offset); } else { wardner_data = wardner_spare_pal_ram_r(offset & 0x1ff); } break; case 0xc000: if (offset < 0x800) { wardner_data = wardner_sharedram_r(offset & 0x7ff); } break; default: break; } } else { unsigned char *wardner_rom = memory_region(REGION_CPU1); int wardner_rombank = 0x8000 * wardner_membank; wardner_data = wardner_rom[wardner_rombank + offset]; } return wardner_data; }
static int scontra_bankedram_r(int offset) { if (palette_selected) return paletteram_r(offset); else return ram[offset]; }
static READ_HANDLER( thunderx_bankedram_r ) { if ((bank & 0x01) == 0) { if (bank & 0x10) return unknownram[offset]; else return paletteram_r(offset); } else return ram[offset]; }
static int thunderx_bankedram_r(int offset) { if ((bank & 0x01) == 0) { if (bank & 0x10) return unknownram[offset]; else return paletteram_r(offset); } else return ram[offset]; }
static READ8_HANDLER( bankedram_r ) { if (rambank == 2) return cbasebal_textram_r(offset); /* VRAM */ else if (rambank == 1) { if (offset < 0x800) return paletteram_r(offset); else return 0; } else { return cbasebal_scrollram_r(offset); /* SCROLL */ } }
static READ_HANDLER( thunderx_bankedram_r ) { if (rambank & 0x01) return ram[offset]; else if (rambank & 0x10) { if (pmcbank) { // logerror("%04x read pmcram %04x\n",activecpu_get_pc(),offset); return pmcram[offset]; } else { logerror("%04x read pmc internal ram %04x\n",activecpu_get_pc(),offset); return 0; } } else return paletteram_r(offset); }
static READ8_HANDLER( spy_bankedram1_r ) { if (rambank & 1) { return paletteram_r(offset); } else if (rambank & 2) { if (pmcbank) { /*logerror("%04x read pmcram %04x\n",activecpu_get_pc(),offset); */ return pmcram[offset]; } else { /*logerror("%04x read pmc internal ram %04x\n",activecpu_get_pc(),offset); */ return 0; } } else return ram[offset]; }
int mgakuen_paletteram_r(int offset) { return paletteram_r(offset); }
int pang_paletteram_r(int offset) { if (paletteram_bank) return paletteram_r(offset + 0x800); return paletteram_r(offset); }
static READ8_HANDLER( le_4800_r ) { if (cur_control2 & 0x10) /* RAM enable */ { return paletteram_r(offset); } else { if (offset < 0x0800) { switch (offset) { case 0x40: case 0x41: case 0x42: case 0x43: case 0x44: case 0x45: case 0x46: return K053244_r(offset-0x40); break; case 0x80: case 0x81: case 0x82: case 0x83: case 0x84: case 0x85: case 0x86: case 0x87: case 0x88: case 0x89: case 0x8a: case 0x8b: case 0x8c: case 0x8d: case 0x8e: case 0x8f: case 0x90: case 0x91: case 0x92: case 0x93: case 0x94: case 0x95: case 0x96: case 0x97: case 0x98: case 0x99: case 0x9a: case 0x9b: case 0x9c: case 0x9d: case 0x9e: case 0x9f: return K054000_r(offset-0x80); break; case 0xca: return sound_status_r(0); break; } } else if (offset < 0x1800) return K053245_r((offset - 0x0800) & 0x07ff); else if (offset < 0x2000) return K056832_ram_code_lo_r(offset - 0x1800); else if (offset < 0x2800) return K056832_ram_code_hi_r(offset - 0x2000); else if (offset < 0x3000) return K056832_ram_attr_lo_r(offset - 0x2800); else /* (offset < 0x3800) */ return K056832_ram_attr_hi_r(offset - 0x3000); } return 0; }