int mipi_dsi_set_timing(struct platform_device *pdev)
{
int ret = 0;
struct balong_fb_data_type *balongfd = NULL;
u32 hline_time = 0;
u32 hsa_time = 0;
u32 hbp_time = 0;
u32 pixel_clk = 0;
struct mipi_dsi_phy_register phy_ctrl = {0};
if (NULL == pdev) {
balongfb_loge("NULL Pointer\n");
return -EINVAL;
}
balongfd = (struct balong_fb_data_type *)platform_get_drvdata(pdev);
if (NULL == balongfd) {
balongfb_loge("NULL Pointer\n");
return -EINVAL;
}
get_dsi_phy_register(&(balongfd->panel_info.mipi.dphy_freq), &phy_ctrl);
set_MIPIDSI_VID_PKT_SIZE( balongfd->panel_info.xres );
pixel_clk = balongfd->panel_info.clk_rate / 1000000;
hsa_time = balongfd->panel_info.ldi.h_pulse_width * phy_ctrl.lane_byte_clk / pixel_clk;
hbp_time = balongfd->panel_info.ldi.h_back_porch * phy_ctrl.lane_byte_clk / pixel_clk;
hline_time = (balongfd->panel_info.ldi.h_pulse_width + balongfd->panel_info.ldi.h_back_porch +
balongfd->panel_info.xres + balongfd->panel_info.ldi.h_front_porch) *
phy_ctrl.lane_byte_clk / pixel_clk;
set_MIPIDSI_VID_HSA_TIME( hsa_time );
set_MIPIDSI_VID_HBP_TIME( hbp_time );
set_MIPIDSI_VID_HLINE_TIME( hline_time );
if (balongfd->panel_info.ldi.v_pulse_width > 15)
balongfd->panel_info.ldi.v_pulse_width = 15;
set_MIPIDSI_VID_VSA_LINES( balongfd->panel_info.ldi.v_pulse_width );
set_MIPIDSI_VID_VBP_LINES( balongfd->panel_info.ldi.v_back_porch );
set_MIPIDSI_VID_VFP_LINES( balongfd->panel_info.ldi.v_front_porch );
set_MIPIDSI_VID_VACTIVE_LINES( balongfd->panel_info.yres );
ret = panel_next_set_timing(pdev);
return ret;
}
static int ldi_set_timing(struct platform_device *pdev)
{
int ret = 0;
struct k3_fb_data_type *k3fd = NULL;
struct k3_panel_info *pinfo = NULL;
u32 edc_base = 0;
BUG_ON(pdev == NULL);
k3fd = (struct k3_fb_data_type *)platform_get_drvdata(pdev);
BUG_ON(k3fd == NULL);
pinfo = &(k3fd->panel_info);
edc_base = k3fd->edc_base;
set_LDI_HRZ_CTRL0_hfp(edc_base, pinfo->ldi.h_front_porch);
set_LDI_HRZ_CTRL0_hbp(edc_base, pinfo->ldi.h_back_porch);
set_LDI_HRZ_CTRL1_hsw(edc_base, pinfo->ldi.h_pulse_width);
set_LDI_VRT_CTRL0_vfp(edc_base, pinfo->ldi.v_front_porch);
set_LDI_VRT_CTRL0_vbp(edc_base, pinfo->ldi.v_back_porch);
if (pinfo->ldi.v_pulse_width > 15)
pinfo->ldi.v_pulse_width = 15;
set_LDI_VRT_CTRL1_vsw(edc_base, pinfo->ldi.v_pulse_width);
set_LDI_DSP_SIZE_hsize(edc_base, pinfo->xres);
set_LDI_DSP_SIZE_vsize(edc_base, pinfo->yres);
set_LDI_PLR_CTRL_hsync(edc_base, pinfo->ldi.hsync_plr);
set_LDI_PLR_CTRL_vsync(edc_base, pinfo->ldi.vsync_plr);
if (clk_set_rate(k3fd->ldi_clk, pinfo->clk_rate) != 0) {
k3fb_loge("failed to set ldi clk rate(%d).\n", pinfo->clk_rate);
}
ret = panel_next_set_timing(pdev);
return ret;
}
