int pci_host_common_probe(struct platform_device *pdev, struct pci_ecam_ops *ops) { const char *type; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct pci_bus *bus, *child; struct pci_config_window *cfg; struct list_head resources; type = of_get_property(np, "device_type", NULL); if (!type || strcmp(type, "pci")) { dev_err(dev, "invalid \"device_type\" %s\n", type); return -EINVAL; } of_pci_check_probe_only(); /* Parse and map our Configuration Space windows */ INIT_LIST_HEAD(&resources); cfg = gen_pci_init(dev, &resources, ops); if (IS_ERR(cfg)) return PTR_ERR(cfg); /* Do not reassign resources if probe only */ if (!pci_has_flag(PCI_PROBE_ONLY)) pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS); bus = pci_scan_root_bus(dev, cfg->busr.start, &ops->pci_ops, cfg, &resources); if (!bus) { dev_err(dev, "Scanning rootbus failed"); return -ENODEV; } pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); /* * We insert PCI resources into the iomem_resource and * ioport_resource trees in either pci_bus_claim_resources() * or pci_bus_assign_resources(). */ if (pci_has_flag(PCI_PROBE_ONLY)) { pci_bus_claim_resources(bus); } else { pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); list_for_each_entry(child, &bus->children, node) pcie_bus_configure_settings(child); } pci_bus_add_devices(bus); return 0; }
int __ref shpchp_configure_device(struct slot *p_slot) { struct pci_dev *dev; struct pci_bus *parent = p_slot->ctrl->pci_dev->subordinate; int num, fn; struct controller *ctrl = p_slot->ctrl; dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, 0)); if (dev) { ctrl_err(ctrl, "Device %s already exists " "at %04x:%02x:%02x, cannot hot-add\n", pci_name(dev), pci_domain_nr(parent), p_slot->bus, p_slot->device); pci_dev_put(dev); return -EINVAL; } num = pci_scan_slot(parent, PCI_DEVFN(p_slot->device, 0)); if (num == 0) { ctrl_err(ctrl, "No new device found\n"); return -ENODEV; } for (fn = 0; fn < 8; fn++) { dev = pci_get_slot(parent, PCI_DEVFN(p_slot->device, fn)); if (!dev) continue; if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { /* Find an unused bus number for the new bridge */ struct pci_bus *child; unsigned char busnr, start = parent->secondary; unsigned char end = parent->subordinate; for (busnr = start; busnr <= end; busnr++) { if (!pci_find_bus(pci_domain_nr(parent), busnr)) break; } if (busnr > end) { ctrl_err(ctrl, "No free bus for hot-added bridge\n"); pci_dev_put(dev); continue; } child = pci_add_new_bus(parent, dev, busnr); if (!child) { ctrl_err(ctrl, "Cannot add new bus for %s\n", pci_name(dev)); pci_dev_put(dev); continue; } child->subordinate = pci_do_scan_bus(child); pci_bus_size_bridges(child); } pci_configure_slot(dev); pci_dev_put(dev); } pci_bus_assign_resources(parent); pci_bus_add_devices(parent); pci_enable_bridges(parent); return 0; }
int __ref cpci_configure_slot(struct slot *slot) { struct pci_bus *parent; int fn; dbg("%s - enter", __func__); if (slot->dev == NULL) { dbg("pci_dev null, finding %02x:%02x:%x", slot->bus->number, PCI_SLOT(slot->devfn), PCI_FUNC(slot->devfn)); slot->dev = pci_get_slot(slot->bus, slot->devfn); } /* Still NULL? Well then scan for it! */ if (slot->dev == NULL) { int n; dbg("pci_dev still null"); /* * This will generate pci_dev structures for all functions, but * we will only call this case when lookup fails. */ n = pci_scan_slot(slot->bus, slot->devfn); dbg("%s: pci_scan_slot returned %d", __func__, n); slot->dev = pci_get_slot(slot->bus, slot->devfn); if (slot->dev == NULL) { err("Could not find PCI device for slot %02x", slot->number); return -ENODEV; } } parent = slot->dev->bus; for (fn = 0; fn < 8; fn++) { struct pci_dev *dev; dev = pci_get_slot(parent, PCI_DEVFN(PCI_SLOT(slot->devfn), fn)); if (!dev) continue; if ((dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) || (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)) { /* Find an unused bus number for the new bridge */ struct pci_bus *child; unsigned char busnr, start = parent->secondary; unsigned char end = parent->subordinate; for (busnr = start; busnr <= end; busnr++) { if (!pci_find_bus(pci_domain_nr(parent), busnr)) break; } if (busnr >= end) { err("No free bus for hot-added bridge\n"); pci_dev_put(dev); continue; } child = pci_add_new_bus(parent, dev, busnr); if (!child) { err("Cannot add new bus for %s\n", pci_name(dev)); pci_dev_put(dev); continue; } child->subordinate = pci_do_scan_bus(child); pci_bus_size_bridges(child); } pci_dev_put(dev); } pci_bus_assign_resources(parent); pci_bus_add_devices(parent); pci_enable_bridges(parent); dbg("%s - exit", __func__); return 0; }
static int __init mcf_pci_init(void) { pr_info("ColdFire: PCI bus initialization...\n"); /* Reset the external PCI bus */ __raw_writel(PCIGSCR_RESET, PCIGSCR); __raw_writel(0, PCITCR); request_resource(&iomem_resource, &mcf_pci_mem); request_resource(&iomem_resource, &mcf_pci_io); /* Configure PCI arbiter */ __raw_writel(PACR_INTMPRI | PACR_INTMINTE | PACR_EXTMPRI(0x1f) | PACR_EXTMINTE(0x1f), PACR); /* Set required multi-function pins for PCI bus use */ __raw_writew(0x3ff, MCFGPIO_PAR_PCIBG); __raw_writew(0x3ff, MCFGPIO_PAR_PCIBR); /* Set up config space for local host bus controller */ __raw_writel(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE, PCISCR); __raw_writel(PCICR1_LT(32) | PCICR1_CL(8), PCICR1); __raw_writel(0, PCICR2); /* * Set up the initiator windows for memory and IO mapping. * These give the CPU bus access onto the PCI bus. One for each of * PCI memory and IO address spaces. */ __raw_writel(WXBTAR(PCI_MEM_PA, PCI_MEM_BA, PCI_MEM_SIZE), PCIIW0BTAR); __raw_writel(WXBTAR(PCI_IO_PA, PCI_IO_BA, PCI_IO_SIZE), PCIIW1BTAR); __raw_writel(PCIIWCR_W0_MEM /*| PCIIWCR_W0_MRDL*/ | PCIIWCR_W0_E | PCIIWCR_W1_IO | PCIIWCR_W1_E, PCIIWCR); /* * Set up the target windows for access from the PCI bus back to the * CPU bus. All we need is access to system RAM (for mastering). */ __raw_writel(CONFIG_RAMBASE, PCIBAR1); __raw_writel(CONFIG_RAMBASE | PCITBATR1_E, PCITBATR1); /* Keep a virtual mapping to IO/config space active */ iospace = (unsigned long) ioremap(PCI_IO_PA, PCI_IO_SIZE); if (iospace == 0) return -ENODEV; pr_info("Coldfire: PCI IO/config window mapped to 0x%x\n", (u32) iospace); /* Turn of PCI reset, and wait for devices to settle */ __raw_writel(0, PCIGSCR); set_current_state(TASK_UNINTERRUPTIBLE); schedule_timeout(msecs_to_jiffies(200)); rootbus = pci_scan_bus(0, &mcf_pci_ops, NULL); if (!rootbus) return -ENODEV; rootbus->resource[0] = &mcf_pci_io; rootbus->resource[1] = &mcf_pci_mem; pci_fixup_irqs(pci_common_swizzle, mcf_pci_map_irq); pci_bus_size_bridges(rootbus); pci_bus_assign_resources(rootbus); pci_bus_add_devices(rootbus); return 0; }