/*
* devfn_to_vertex() - returns the vertex of the device given the bus, slot,
* and function numbers.
*/
devfs_handle_t
devfn_to_vertex(unsigned char busnum, unsigned int devfn)
{
int slot = 0;
int func = 0;
char name[16];
devfs_handle_t pci_bus = NULL;
devfs_handle_t device_vertex = (devfs_handle_t)NULL;
/*
* Go get the pci bus vertex.
*/
pci_bus = pci_bus_to_vertex(busnum);
if (!pci_bus) {
/*
* During probing, the Linux pci code invents non-existent
* bus numbers and pci_dev structures and tries to access
* them to determine existence. Don't crib during probing.
*/
if (done_probing)
printk("devfn_to_vertex: Invalid bus number %d given.\n", busnum);
return(NULL);
}
/*
* Go get the slot&function vertex.
* Should call pciio_slot_func_to_name() when ready.
*/
slot = PCI_SLOT(devfn);
func = PCI_FUNC(devfn);
/*
* For a NON Multi-function card the name of the device looks like:
* ../pci/1, ../pci/2 ..
*/
if (func == 0) {
sprintf(name, "%d", slot);
if (hwgraph_traverse(pci_bus, name, &device_vertex) ==
GRAPH_SUCCESS) {
if (device_vertex) {
return(device_vertex);
}
}
}
/*
* This maybe a multifunction card. It's names look like:
* ../pci/1a, ../pci/1b, etc.
*/
sprintf(name, "%d%c", slot, 'a'+func);
if (hwgraph_traverse(pci_bus, name, &device_vertex) != GRAPH_SUCCESS) {
if (!device_vertex) {
return(NULL);
}
}
return(device_vertex);
}
void
pci_fixup_ioc3(struct pci_dev *d)
{
int i;
unsigned int size;
devfs_handle_t bridge_vhdl = pci_bus_to_vertex(d->bus->number);
/* IOC3 only decodes 0x20 bytes of the config space, reading
* beyond that is relatively benign but writing beyond that
* (especially the base address registers) will shut down the
* pci bus...so avoid doing so.
* NOTE: this means we can't program the intr_pin into the device,
* currently we hack this with special code in
* sgi_pci_intr_support()
*/
DBG("pci_fixup_ioc3: Fixing base addresses for ioc3 device %s\n", d->slot_name);
/* I happen to know from the spec that the ioc3 needs only 0xfffff
* The standard pci trick of writing ~0 to the baddr and seeing
* what comes back doesn't work with the ioc3
*/
size = 0xfffff;
d->resource[0].end = (unsigned long) d->resource[0].start + (unsigned long) size;
/*
* Zero out the resource structure .. because we did not go through
* the normal PCI Infrastructure Init, garbbage are left in these
* fileds.
*/
for (i = 1; i <= PCI_ROM_RESOURCE; i++) {
d->resource[i].start = 0UL;
d->resource[i].end = 0UL;
d->resource[i].flags = 0UL;
}
/*
* Hardcode Device 4 register(IOC3 is in Slot 4) to set the
* DEV_DIRECT bit. This will not work if IOC3 is not on Slot
* 4.
*/
DBG("pci_fixup_ioc3: FIXME .. need to take NASID into account when setting IOC3 devreg 0x%x\n", *(volatile u32 *)0xc0000a000f000220);
*(volatile u32 *)0xc0000a000f000220 |= 0x90000;
d->subsystem_vendor = 0;
d->subsystem_device = 0;
}
/*
* sn_pci_fixup() - This routine is called when platform_pci_fixup() is
* invoked at the end of pcibios_init() to link the Linux pci
* infrastructure to SGI IO Infrasturcture - ia64/kernel/pci.c
*
* Other platform specific fixup can also be done here.
*/
void
sn_pci_fixup(int arg)
{
struct list_head *ln;
struct pci_bus *pci_bus = NULL;
struct pci_dev *device_dev = NULL;
struct sn_widget_sysdata *widget_sysdata;
struct sn_device_sysdata *device_sysdata;
#ifdef SN_IOPORTS
unsigned long ioport;
#endif
pciio_intr_t intr_handle;
int cpuid, bit;
devfs_handle_t device_vertex;
pciio_intr_line_t lines;
extern void sn_pci_find_bios(void);
#ifdef CONFIG_IA64_SGI_SN2
extern int numnodes;
int cnode;
#endif /* CONFIG_IA64_SGI_SN2 */
if (arg == 0) {
sn_init_irq_desc();
sn_pci_find_bios();
#ifdef CONFIG_IA64_SGI_SN2
for (cnode = 0; cnode < numnodes; cnode++) {
extern void intr_init_vecblk(nodepda_t *npda, cnodeid_t, int);
intr_init_vecblk(NODEPDA(cnode), cnode, 0);
}
#endif /* CONFIG_IA64_SGI_SN2 */
return;
}
#if 0
{
devfs_handle_t bridge_vhdl = pci_bus_to_vertex(0);
pcibr_soft_t pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
bridge_t *bridge = pcibr_soft->bs_base;
printk("pci_fixup_ioc3: Before devreg fixup\n");
printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
}
#endif
done_probing = 1;
/*
* Initialize the pci bus vertex in the pci_bus struct.
*/
for( ln = pci_root_buses.next; ln != &pci_root_buses; ln = ln->next) {
pci_bus = pci_bus_b(ln);
widget_sysdata = kmalloc(sizeof(struct sn_widget_sysdata),
GFP_KERNEL);
widget_sysdata->vhdl = pci_bus_to_vertex(pci_bus->number);
pci_bus->sysdata = (void *)widget_sysdata;
}
/*
* set the root start and end so that drivers calling check_region()
* won't see a conflict
*/
#ifdef SN_IOPORTS
ioport_resource.start = sn_ioport_num;
ioport_resource.end = 0xffff;
#else
#if defined(CONFIG_IA64_SGI_SN1)
if ( IS_RUNNING_ON_SIMULATOR() ) {
/*
* IDE legacy IO PORTs are supported in Medusa.
* Just open up IO PORTs from 0 .. ioport_resource.end.
*/
ioport_resource.start = 0;
} else {
/*
* We do not support Legacy IO PORT numbers.
*/
ioport_resource.start |= IO_SWIZ_BASE | __IA64_UNCACHED_OFFSET;
}
ioport_resource.end |= (HSPEC_SWIZ_BASE-1) | __IA64_UNCACHED_OFFSET;
#else
// Need something here for sn2.... ZXZXZX
#endif
#endif
/*
* Set the root start and end for Mem Resource.
*/
iomem_resource.start = 0;
iomem_resource.end = 0xffffffffffffffff;
/*
* Initialize the device vertex in the pci_dev struct.
*/
pci_for_each_dev(device_dev) {
unsigned int irq;
int idx;
u16 cmd;
devfs_handle_t vhdl;
unsigned long size;
extern int bit_pos_to_irq(int);
if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
device_dev->device == PCI_DEVICE_ID_SGI_IOC3) {
extern void pci_fixup_ioc3(struct pci_dev *d);
pci_fixup_ioc3(device_dev);
}
/* Set the device vertex */
device_sysdata = kmalloc(sizeof(struct sn_device_sysdata),
GFP_KERNEL);
device_sysdata->vhdl = devfn_to_vertex(device_dev->bus->number, device_dev->devfn);
device_sysdata->isa64 = 0;
/*
* Set the xbridge Device(X) Write Buffer Flush and Xbow Flush
* register addresses.
*/
(void) set_flush_addresses(device_dev, device_sysdata);
device_dev->sysdata = (void *) device_sysdata;
set_sn_pci64(device_dev);
pci_read_config_word(device_dev, PCI_COMMAND, &cmd);
/*
* Set the resources address correctly. The assumption here
* is that the addresses in the resource structure has been
* read from the card and it was set in the card by our
* Infrastructure ..
*/
vhdl = device_sysdata->vhdl;
for (idx = 0; idx < PCI_ROM_RESOURCE; idx++) {
size = 0;
size = device_dev->resource[idx].end -
device_dev->resource[idx].start;
if (size) {
device_dev->resource[idx].start = (unsigned long)pciio_pio_addr(vhdl, 0, PCIIO_SPACE_WIN(idx), 0, size, 0, PCIIO_BYTE_STREAM);
device_dev->resource[idx].start |= __IA64_UNCACHED_OFFSET;
}
else
continue;
device_dev->resource[idx].end =
device_dev->resource[idx].start + size;
#ifdef CONFIG_IA64_SGI_SN1
/*
* Adjust the addresses to go to the SWIZZLE ..
*/
device_dev->resource[idx].start =
device_dev->resource[idx].start & 0xfffff7ffffffffff;
device_dev->resource[idx].end =
device_dev->resource[idx].end & 0xfffff7ffffffffff;
#endif
if (device_dev->resource[idx].flags & IORESOURCE_IO) {
cmd |= PCI_COMMAND_IO;
#ifdef SN_IOPORTS
ioport = sn_allocate_ioports(device_dev->resource[idx].start);
if (ioport < 0) {
printk("sn_pci_fixup: PCI Device 0x%x on PCI Bus %d not mapped to IO PORTs .. IO PORTs exhausted\n", device_dev->devfn, device_dev->bus->number);
continue;
}
pciio_config_set(vhdl, (unsigned) PCI_BASE_ADDRESS_0 + (idx * 4), 4, (res + (ioport & 0xfff)));
printk("sn_pci_fixup: ioport number %d mapped to pci address 0x%lx\n", ioport, (res + (ioport & 0xfff)));
device_dev->resource[idx].start = ioport;
device_dev->resource[idx].end = ioport + SN_IOPORTS_UNIT;
#endif
}
if (device_dev->resource[idx].flags & IORESOURCE_MEM)
cmd |= PCI_COMMAND_MEMORY;
}
/*
* Now handle the ROM resource ..
*/
size = device_dev->resource[PCI_ROM_RESOURCE].end -
device_dev->resource[PCI_ROM_RESOURCE].start;
if (size) {
device_dev->resource[PCI_ROM_RESOURCE].start =
(unsigned long) pciio_pio_addr(vhdl, 0, PCIIO_SPACE_ROM, 0,
size, 0, PCIIO_BYTE_STREAM);
device_dev->resource[PCI_ROM_RESOURCE].start |= __IA64_UNCACHED_OFFSET;
device_dev->resource[PCI_ROM_RESOURCE].end =
device_dev->resource[PCI_ROM_RESOURCE].start + size;
#ifdef CONFIG_IA64_SGI_SN1
/*
* go through synergy swizzled space
*/
device_dev->resource[PCI_ROM_RESOURCE].start &= 0xfffff7ffffffffffUL;
device_dev->resource[PCI_ROM_RESOURCE].end &= 0xfffff7ffffffffffUL;
#endif
}
/*
* Update the Command Word on the Card.
*/
cmd |= PCI_COMMAND_MASTER; /* If the device doesn't support */
/* bit gets dropped .. no harm */
pci_write_config_word(device_dev, PCI_COMMAND, cmd);
pci_read_config_byte(device_dev, PCI_INTERRUPT_PIN, (unsigned char *)&lines);
if (device_dev->vendor == PCI_VENDOR_ID_SGI &&
device_dev->device == PCI_DEVICE_ID_SGI_IOC3 ) {
lines = 1;
}
device_sysdata = (struct sn_device_sysdata *)device_dev->sysdata;
device_vertex = device_sysdata->vhdl;
intr_handle = pciio_intr_alloc(device_vertex, NULL, lines, device_vertex);
bit = intr_handle->pi_irq;
cpuid = intr_handle->pi_cpu;
#ifdef CONFIG_IA64_SGI_SN1
irq = bit_pos_to_irq(bit);
#else /* SN2 */
irq = bit;
#endif
irq = irq + (cpuid << 8);
pciio_intr_connect(intr_handle);
device_dev->irq = irq;
#ifdef ajmtestintr
{
int slot = PCI_SLOT(device_dev->devfn);
static int timer_set = 0;
pcibr_intr_t pcibr_intr = (pcibr_intr_t)intr_handle;
pcibr_soft_t pcibr_soft = pcibr_intr->bi_soft;
extern void intr_test_handle_intr(int, void*, struct pt_regs *);
if (!timer_set) {
intr_test_set_timer();
timer_set = 1;
}
intr_test_register_irq(irq, pcibr_soft, slot);
request_irq(irq, intr_test_handle_intr,0,NULL, NULL);
}
#endif
}
#if 0
{
devfs_handle_t bridge_vhdl = pci_bus_to_vertex(0);
pcibr_soft_t pcibr_soft = (pcibr_soft_t) hwgraph_fastinfo_get(bridge_vhdl);
bridge_t *bridge = pcibr_soft->bs_base;
printk("pci_fixup_ioc3: Before devreg fixup\n");
printk("pci_fixup_ioc3: Devreg 0 0x%x\n", bridge->b_device[0].reg);
printk("pci_fixup_ioc3: Devreg 1 0x%x\n", bridge->b_device[1].reg);
printk("pci_fixup_ioc3: Devreg 2 0x%x\n", bridge->b_device[2].reg);
printk("pci_fixup_ioc3: Devreg 3 0x%x\n", bridge->b_device[3].reg);
printk("pci_fixup_ioc3: Devreg 4 0x%x\n", bridge->b_device[4].reg);
printk("pci_fixup_ioc3: Devreg 5 0x%x\n", bridge->b_device[5].reg);
printk("pci_fixup_ioc3: Devreg 6 0x%x\n", bridge->b_device[6].reg);
printk("pci_fixup_ioc3: Devreg 7 0x%x\n", bridge->b_device[7].reg);
}
printk("testing Big Window: 0xC0000200c0000000 %p\n", *( (volatile uint64_t *)0xc0000200a0000000));
printk("testing Big Window: 0xC0000200c0000008 %p\n", *( (volatile uint64_t *)0xc0000200a0000008));
#endif
}
