static void
qpi_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
u_int reg, uint32_t data, int bytes)
{
pci_cfgregwrite(bus, slot, func, reg, data, bytes);
}
ACPI_STATUS
AcpiOsWritePciConfiguration(ACPI_PCI_ID *PciId, UINT32 Register,
UINT64 Value, UINT32 Width)
{
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register,
(uint32_t)Value, Width / 8); /* XXX casting */
return (AE_OK);
}
ACPI_STATUS
AcpiOsWritePciConfiguration (
ACPI_PCI_ID *PciId,
UINT32 Register,
ACPI_INTEGER Value,
UINT32 Width)
{
u_int32_t byte_width = Width / 8;
if (!pci_cfgregopen())
return(AE_NOT_EXIST);
pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register, Value, byte_width);
return(AE_OK);
}
ACPI_STATUS
AcpiOsWritePciConfiguration (ACPI_PCI_ID *PciId, UINT32 Register,
UINT64 Value, UINT32 Width)
{
#ifdef __aarch64__
/* ARM64TODO: Add pci support */
return (AE_SUPPORT);
#else
if (Width == 64)
return (AE_SUPPORT);
if (!pci_cfgregopen())
return (AE_NOT_EXIST);
pci_cfgregwrite(PciId->Bus, PciId->Device, PciId->Function, Register,
Value, Width / 8);
return (AE_OK);
#endif
}
void
legacy_pcib_write_config(device_t dev, int bus, int slot, int func,
int reg, u_int32_t data, int bytes)
{
pci_cfgregwrite(bus, slot, func, reg, data, bytes);
}
void pcicfg_write_dword(HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U32 v)
{
pci_cfgregwrite(bus, dev, func, reg, v, 4);
}/* PCI space access */
void pcicfg_write_byte (HPT_U8 bus, HPT_U8 dev, HPT_U8 func, HPT_U8 reg, HPT_U8 v)
{
pci_cfgregwrite(bus, dev, func, reg, v, 1);
}