static uint8_t *readAtomBIOS(pci_dt_t *ati_dev)
{
uint32_t bar[7];
uint32_t *BIOSBase;
uint32_t counter;
volatile uint32_t *regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (volatile uint32_t *) (bar[2] & ~0x0f);
accessROM(ati_dev, 0);
REG32W(0xa8, 0);
REG32R(0xac);
REG32W(0xa8, 0);
REG32R(0xac);
BIOSBase = malloc(0x10000);
REG32W(0xa8, 0);
BIOSBase[0] = REG32R(0xac);
counter = 4;
do {
REG32W(0xa8, counter);
BIOSBase[counter/4] = REG32R(0xac);
counter +=4;
} while (counter != 0x10000);
accessROM((pci_dt_t *)regs, 1);
if (*(uint16_t *)BIOSBase != 0xAA55) {
printf("Wrong BIOS signature: %04x\n", *(uint16_t *)BIOSBase);
return 0;
}
return (uint8_t *)BIOSBase;
}
static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
int where, int size, u32 *value)
{
struct pci_pbm_info *pbm = bus_dev->sysdata;
unsigned char bus = bus_dev->number;
u32 *addr;
u16 tmp16;
u8 tmp8;
switch (size) {
case 1:
*value = 0xff;
break;
case 2:
*value = 0xffff;
break;
case 4:
*value = 0xffffffff;
break;
}
addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
if (!addr)
return PCIBIOS_SUCCESSFUL;
if (__sabre_out_of_range(pbm, bus, devfn))
return PCIBIOS_SUCCESSFUL;
switch (size) {
case 1:
pci_config_read8((u8 *) addr, &tmp8);
*value = tmp8;
break;
case 2:
if (where & 0x01) {
printk("pci_read_config_word: misaligned reg [%x]\n",
where);
return PCIBIOS_SUCCESSFUL;
}
pci_config_read16((u16 *) addr, &tmp16);
*value = tmp16;
break;
case 4:
if (where & 0x03) {
printk("pci_read_config_dword: misaligned reg [%x]\n",
where);
return PCIBIOS_SUCCESSFUL;
}
pci_config_read32(addr, value);
break;
}
return PCIBIOS_SUCCESSFUL;
}
uint32_t getvramsizekb(pci_dt_t *ati_dev)
{
uint32_t bar[7];
uint32_t size;
volatile uint32_t *regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (ati_dev->device_id < 0x9400) {
size = (REG32R(R5XX_CONFIG_MEMSIZE)) >> 10;
} else {
static uint32_t accessROM(pci_dt_t *ati_dev, unsigned int mode)
{
uint32_t bar[7];
volatile uint32_t *regs;
bar[2] = pci_config_read32(ati_dev->dev.addr, 0x18 );
regs = (uint32_t *) (bar[2] & ~0x0f);
if (mode) {
if (mode != 1) {
return 0xe00002c7;
}
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1600, 0x14030300);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x17a0, 0x21);
REG32W(0x1798, 0x21);
REG32W(0x1798, 0x21);
} else {
REG32W(0x1600, 0x14030302);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00080000);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x00080721);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
REG32W(0x1604, 0x0400e9fc);
REG32W(0x161c, 0x00);
REG32W(0x1620, 0x9f);
REG32W(0x1618, 0x00040004);
REG32W(0x161c, 0x00);
REG32W(0x1604, 0xe9fc);
REG32W(0x179c, 0x00080000);
REG32W(0x1798, 0x00080721);
REG32W(0x17a0, 0x00080621);
REG32W(0x1798, 0x21);
REG32W(0x17a0, 0x21);
REG32W(0x179c, 0x00);
}
return 0;
}
static void read_smb_intel(pci_dt_t *smbus_dev)
{
int i, speed;
uint8_t spd_size, spd_type;
uint32_t base, mmio, hostc;
// bool dump = false;
RamSlotInfo_t* slot;
uint16_t cmd = pci_config_read16(smbus_dev->dev.addr, 0x04);
DBG("SMBus CmdReg: 0x%x\n", cmd);
pci_config_write16(smbus_dev->dev.addr, 0x04, cmd | 1);
mmio = pci_config_read32(smbus_dev->dev.addr, 0x10);// & ~0x0f;
base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;
hostc = pci_config_read8(smbus_dev->dev.addr, 0x40);
IOLog("Scanning SMBus [%04x:%04x], mmio: 0x%x, ioport: 0x%x, hostc: 0x%x\n",
smbus_dev->vendor_id, smbus_dev->device_id, mmio, base, hostc);
// Search MAX_RAM_SLOTS slots
// for (i = 0; i < MAX_RAM_SLOTS; i++){
// spd_size = smb_read_byte_intel(base, 0x50 + i, 0);
} // for
/** Add a new PCI ATA device.
* @param device Device that was matched.
* @param data Unused.
* @return Whether the device has been claimed. */
static bool pci_ata_add_device(pci_device_t *device, void *data) {
uint32_t ctrl_base, cmd_base, bus_master_base, irq;
ata_channel_t *pri, *sec;
uint8_t pri_pi, sec_pi;
kprintf(LOG_NOTICE, "ata: found PCI ATA controller %d:%02x.%d (vendor: 0x%04x, id: 0x%04x)\n",
device->bus, device->device, device->function, device->vendor_id,
device->device_id);
/* Get the programming interface so we can find out what mode the
* channels are operating in. The primary channel's interface is in the
* lower 2 bits, so we clear the higher 2 bits to find it. The secondary
* channel's interface, obviously, is in the higher 2 bits, so we we
* shift it right by 2 bits. */
pri_pi = (device->prog_iface & 0x0F) & ~0x0C;
sec_pi = (device->prog_iface & 0x0F) >> 2;
/* Get the bus master base. */
bus_master_base = pci_config_read32(device, PCI_CONFIG_BAR4) & PCI_IO_ADDRESS_MASK;
/* Get primary channel details and add it. */
if(PCI_ATA_IS_COMPAT(pri_pi)) {
/* Compatibility mode channels always have the same details. */
ctrl_base = 0x3F6;
cmd_base = 0x1F0;
irq = 14;
} else {
/* Quote: "Base registers used to map Control Block registers
* must ask for 4 bytes of IO space. In this four byte
* allocation the byte at offset 02h is where the Alternate
* Status/Device Control byte is located.". Therefore, add 2
* to the value read. */
ctrl_base = (pci_config_read32(device, PCI_CONFIG_BAR1) & PCI_IO_ADDRESS_MASK) + 2;
cmd_base = (pci_config_read32(device, PCI_CONFIG_BAR0) & PCI_IO_ADDRESS_MASK);
irq = device->interrupt_line;
}
/* Add the channel. */
pri = pci_ata_channel_add(device, 0, ctrl_base, cmd_base, bus_master_base, irq);
if(pri) {
kprintf(LOG_NOTICE, " primary: %s (ctrl_base: 0x%x, cmd_base: 0x%x, bm_base: 0x%x, irq: %d)\n",
PCI_ATA_IS_COMPAT(pri_pi) ? "compat" : "native-PCI",
ctrl_base, cmd_base, bus_master_base, irq);
}
/* Now the secondary channel. */
if(PCI_ATA_IS_COMPAT(sec_pi)) {
ctrl_base = 0x376;
cmd_base = 0x170;
irq = 15;
} else {
/* Same as above. */
ctrl_base = (pci_config_read32(device, PCI_CONFIG_BAR3) & PCI_IO_ADDRESS_MASK) + 2;
cmd_base = (pci_config_read32(device, PCI_CONFIG_BAR2) & PCI_IO_ADDRESS_MASK);
irq = device->interrupt_line;
}
/* Add the channel. */
sec = pci_ata_channel_add(device, 1, ctrl_base, cmd_base, bus_master_base, irq);
if(sec) {
kprintf(LOG_NOTICE, " secondary: %s (ctrl_base: 0x%x, cmd_base: 0x%x, bm_base: 0x%x, irq: %d)\n",
PCI_ATA_IS_COMPAT(pri_pi) ? "compat" : "native-PCI",
ctrl_base, cmd_base, bus_master_base + 8, irq);
}
/* Scan for devices. */
if(pri) { ata_channel_scan(pri); }
if(sec) { ata_channel_scan(sec); }
return true;
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
char *devicepath;
volatile uint8_t *regs;
uint32_t bar[7];
char *model;
uint8_t BuiltIn = 0x00;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
unsigned int device_id;
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
device_id = gma_dev->device_id;
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if (!device)
{
printf("Failed initializing dev-prop string dev-entry.\n");
pause();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if ((model == (char *)&"Mobile GMA950")
|| (model == (char *)&"Mobile GMA3150"))
{
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if ((model == (char *)&"Desktop GMA950")
|| (model == (char *)&"Desktop GMA3150"))
{
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if (model == (char *)&"GMAX3100")
{
devprop_add_value(device, "AAPL,HasPanel", GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported", GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected", GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control", GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity", GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify", GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth", GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither", GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink", GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height", GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace", GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter", GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent", GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency", GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat", GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType", GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe", GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat", GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh", GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch", GMAX3100_vals[21], 4);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if (model == (char *)&"HD Graphics 2000 Mobile")
{
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL00,PixelFormat", HD2000_vals[0], 4);
devprop_add_value(device, "AAPL00,T1", HD2000_vals[1], 4);
devprop_add_value(device, "AAPL00,T2", HD2000_vals[2], 4);
devprop_add_value(device, "AAPL00,T3", HD2000_vals[3], 4);
devprop_add_value(device, "AAPL00,T4", HD2000_vals[4], 4);
devprop_add_value(device, "AAPL00,T5", HD2000_vals[5], 4);
devprop_add_value(device, "AAPL00,T6", HD2000_vals[6], 4);
devprop_add_value(device, "AAPL00,T7", HD2000_vals[7], 4);
devprop_add_value(device, "AAPL00,LinkType", HD2000_vals[8], 4);
devprop_add_value(device, "AAPL00,LinkFormat", HD2000_vals[9], 4);
devprop_add_value(device, "AAPL00,DualLink", HD2000_vals[10], 4);
devprop_add_value(device, "AAPL00,Dither", HD2000_vals[11], 4);
devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4);
devprop_add_value(device, "graphic-options", HD2000_vals[13], 4);
devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20);
}
else if (model == (char *)&"HD Graphics 3000 Mobile")
{
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL00,PixelFormat", HD3000_vals[0], 4);
devprop_add_value(device, "AAPL00,T1", HD3000_vals[1], 4);
devprop_add_value(device, "AAPL00,T2", HD3000_vals[2], 4);
devprop_add_value(device, "AAPL00,T3", HD3000_vals[3], 4);
devprop_add_value(device, "AAPL00,T4", HD3000_vals[4], 4);
devprop_add_value(device, "AAPL00,T5", HD3000_vals[5], 4);
devprop_add_value(device, "AAPL00,T6", HD3000_vals[6], 4);
devprop_add_value(device, "AAPL00,T7", HD3000_vals[7], 4);
devprop_add_value(device, "AAPL00,LinkType", HD3000_vals[8], 4);
devprop_add_value(device, "AAPL00,LinkFormat", HD3000_vals[9], 4);
devprop_add_value(device, "AAPL00,DualLink", HD3000_vals[10], 4);
devprop_add_value(device, "AAPL00,Dither", HD3000_vals[11], 4);
devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4);
devprop_add_value(device, "graphic-options", HD3000_vals[13], 4);
devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20);
}
else if (model == (char *)&"HD Graphics 2000")
{
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id));
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20);
}
else if (model == (char *)&"HD Graphics 3000")
{
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
device_id = 0x00000126; // Inject a valid mobile GPU device id instead of patching kexts
devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id));
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20);
}
else if(model == (char*)&"HD Graphics 4000" ||
model == (char*)&"HD Graphics 4000 Mobile")
{
uint32_t ram = (((getVBEVideoRam() + 512) / 1024) + 512) / 1024;
uint32_t ig_platform_id;
switch (ram)
{
case 96:
ig_platform_id = 0x01660000; // 96mb
break;
case 64:
ig_platform_id = 0x01660009; // 64mb
break;
case 32:
ig_platform_id = 0x01620005; // 32mb
break;
default:
printf("Please specify 96, 64, or 32MB RAM for the HD4000 in the bios.\n"
"The selected %dMB RAM configuration is not supported for the HD4000.\n", ram);
pause();
return false; // Exit early before the AAPL,ig-platform-id property is set.
break;
}
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t*)&ig_platform_id, 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if (!stringdata)
{
printf("No stringdata.\n");
pause();
return false;
}
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
bool getSMBOemProcessorBusSpeed(returnType *value)
{
if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_DOTHAN: // Intel Pentium M
case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM: // Intel Atom (45nm)
return false;
case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7
{
// thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
value->word = qpibusspeed;
return true;
}
}
}
}
}
return false;
}
static int sm_get_bus_speed (const char *name, int table_num)
{
if (Platform.CPU.Vendor == 0x756E6547) // Intel
{
switch (Platform.CPU.Family)
{
case 0x06:
{
switch (Platform.CPU.Model)
{
case CPU_MODEL_PENTIUM_M: // Pentium M 0x0D
case CPU_MODEL_YONAH: // Yonah 0x0E
case CPU_MODEL_MEROM: // Merom 0x0F
case CPU_MODEL_PENRYN: // Penryn 0x17
case CPU_MODEL_ATOM: // Atom 45nm 0x1C
return 0; // TODO: populate bus speed for these processors
// case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
// if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))
// return 2500; // Core i5
// return 4800; // Core i7
// case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
// case CPU_MODEL_NEHALEM_EX:
// case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
// return 4800; // GT/s / 1000
//
case CPU_MODEL_WESTMERE_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
return 0; // TODO: populate bus speed for these processors
// case 0x19: // Intel Core i5 650 @3.20 Ghz
// return 2500; // why? Intel spec says 2.5GT/s
case 0x19: // Intel Core i5 650 @3.20 Ghz
case CPU_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)
case CPU_MODEL_DALES: // Intel Core i5, i7 LGA1156 (45nm) ???
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5, i7 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Core i7 LGA1366 (45nm) 6 Core ???
{ // thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < sizeof(possible_nhm_bus); i++)
{
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00)
nhm_bus = possible_nhm_bus[i];
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;
DBG("qpibusspeed %d\n", qpibusspeed);
return qpibusspeed;
}
}
}
}
}
return 0;
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
char *devicepath = NULL;
volatile uint8_t *regs;
uint32_t bar[7];
char *model = NULL;
uint8_t BuiltIn = 0x00;
uint16_t vendor_id = gma_dev->vendor_id;
uint16_t device_id = gma_dev->device_id;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
int n_igs = 0;
int len;
const char *value;
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_controller_name(device_id, vendor_id);
verbose("---------------------------------------------\n");
verbose("------------ INTEL DEVICE INFO --------------\n");
verbose("---------------------------------------------\n");
verbose("Class code: [%04x]\n%s [%04x:%04x] (rev %02x)\nSubsystem: [%04x:%04x] :: %s\n",
gma_dev->class_id, model, gma_dev->vendor_id, gma_dev->device_id, gma_dev->revision_id, gma_dev->subsys_id.subsys.vendor_id, gma_dev->subsys_id.subsys.device_id, devicepath);
if (!string) {
string = devprop_create_string();
}
struct DevPropDevice *device = devprop_add_device(string, devicepath);
if (!device) {
printf("Failed initializing dev-prop string dev-entry.\n");
pause();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
switch ((device_id << 16) | vendor_id)
{
case GMA_IRONLAKE_D_G: // 0042
case GMA_IRONLAKE_M_G: // 0046
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL,os-info", HDx000_os_info, 20);
break;
/* 27A2, 27AE, 27A6, A001, A011, A012, */
case GMA_I945_GM: // Mobile GMA950 Mobile GMA3150
case GMA_I945_GME:
//case GMA_945GM:
case GMA_PINEVIEW_G:
case GMA_PINEVIEW_M:
case GMA_GMA3150_M:
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
break;
/* 2772 ,2776, A002 */
case GMA_I945_G: // Desktop GMA950 Desktop GMA3150
//case GMA_82945G:
case GMA_GMA3150_D:
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
break;
/* 2A02, 2A12, 2A13, 2A42, 2A43 */
case GMA_I965_GM: // GMAX3100
case GMA_I965_GME:
//case 0x80862A13:
case GMA_GM45_GM:
//case GMA_GM45_GM2:
devprop_add_value(device, "AAPL,HasPanel", GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported", GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected", GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control", GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity", GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify", GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth", GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither", GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink", GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height", GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace", GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter", GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent", GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency", GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat", GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType", GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe", GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat", GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh", GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch", GMAX3100_vals[21], 4);
//devprop_add_value(device, "AAPL01,InverterFrequency", GMAX3100_vals[22], 4);
devprop_add_value(device, "class-code", ClassFix, 4);
break;
/* 0106 */
case GMA_SANDYBRIDGE_M_GT1: // HD Graphics 2000 Mobile
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL00,PixelFormat", HD2000_vals[0], 4);
devprop_add_value(device, "AAPL00,T1", HD2000_vals[1], 4);
devprop_add_value(device, "AAPL00,T2", HD2000_vals[2], 4);
devprop_add_value(device, "AAPL00,T3", HD2000_vals[3], 4);
devprop_add_value(device, "AAPL00,T4", HD2000_vals[4], 4);
devprop_add_value(device, "AAPL00,T5", HD2000_vals[5], 4);
devprop_add_value(device, "AAPL00,T6", HD2000_vals[6], 4);
devprop_add_value(device, "AAPL00,T7", HD2000_vals[7], 4);
devprop_add_value(device, "AAPL00,LinkType", HD2000_vals[8], 4);
devprop_add_value(device, "AAPL00,LinkFormat", HD2000_vals[9], 4);
devprop_add_value(device, "AAPL00,DualLink", HD2000_vals[10], 4);
devprop_add_value(device, "AAPL00,Dither", HD2000_vals[11], 4);
devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4);
devprop_add_value(device, "graphic-options", HD2000_vals[13], 4);
devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20);
break;
/* 0116, 0126 */
case GMA_SANDYBRIDGE_M_GT2: // HD Graphics 3000 Mobile
case GMA_SANDYBRIDGE_M_GT2_PLUS:
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL00,PixelFormat", HD3000_vals[0], 4);
devprop_add_value(device, "AAPL00,T1", HD3000_vals[1], 4);
devprop_add_value(device, "AAPL00,T2", HD3000_vals[2], 4);
devprop_add_value(device, "AAPL00,T3", HD3000_vals[3], 4);
devprop_add_value(device, "AAPL00,T4", HD3000_vals[4], 4);
devprop_add_value(device, "AAPL00,T5", HD3000_vals[5], 4);
devprop_add_value(device, "AAPL00,T6", HD3000_vals[6], 4);
devprop_add_value(device, "AAPL00,T7", HD3000_vals[7], 4);
devprop_add_value(device, "AAPL00,LinkType", HD3000_vals[8], 4);
devprop_add_value(device, "AAPL00,LinkFormat", HD3000_vals[9], 4);
devprop_add_value(device, "AAPL00,DualLink", HD3000_vals[10], 4);
devprop_add_value(device, "AAPL00,Dither", HD3000_vals[11], 4);
devprop_add_value(device, "AAPL00,DataJustify", HD3000_vals[12], 4);
devprop_add_value(device, "graphic-options", HD3000_vals[13], 4);
devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20);
devprop_add_value(device, "AAPL,snb-platform-id", HD3000_vals[16], 4);// previusly commented
break;
/* 0102 */
/* HD Graphics 2000 */
case GMA_SANDYBRIDGE_GT1: // 0102
device_id = 0x00000102; // Inject a valid mobile GPU device id instead of patching kexts
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id));
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL,tbl-info", HD2000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD2000_os_info, 20);
break;
/* Sandy Bridge */
/* HD Graphics 3000 */
case GMA_SANDYBRIDGE_GT2: // 0112
case GMA_SANDYBRIDGE_GT2_PLUS: // 0122
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
device_id = 0x00000126; // Inject a valid mobile GPU device id instead of patching kexts
devprop_add_value(device, "device-id", (uint8_t*)&device_id, sizeof(device_id));
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
devprop_add_value(device, "AAPL,tbl-info", HD3000_tbl_info, 18);
devprop_add_value(device, "AAPL,os-info", HD3000_os_info, 20);
break;
/* Ivy Bridge */
/* HD Graphics 4000, HD Graphics 4000 Mobile, HD Graphics P4000, HD Graphics 2500 HD, Graphics 2500 Mobile */
case GMA_IVYBRIDGE_D_GT1: // 0152
case GMA_IVYBRIDGE_M_GT1: // 0156
case GMA_IVYBRIDGE_S_GT1: // 015A
case GMA_IVYBRIDGE_S_GT3: // 015e
case GMA_IVYBRIDGE_D_GT2: // 0162
case GMA_IVYBRIDGE_M_GT2: // 0166
case GMA_IVYBRIDGE_S_GT2: // 016A
case GMA_IVYBRIDGE_S_GT4: // 0172
case GMA_IVYBRIDGE_S_GT5: // 0176
if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_IVY * 2)
{
uint8_t new_aapl0[AAPL_LEN_IVY];
if (hex2bin(value, new_aapl0, AAPL_LEN_IVY) == 0)
{
memcpy(default_aapl_ivy, new_aapl0, AAPL_LEN_IVY);
verbose("Using user supplied AAPL,ig-platform-id\n");
verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",
default_aapl_ivy[0], default_aapl_ivy[1], default_aapl_ivy[2], default_aapl_ivy[3]);
}
devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_ivy, AAPL_LEN_IVY);
}
else if (getIntForKey(kIntelCapriFB, &n_igs, &bootInfo->chameleonConfig))
{
if ((n_igs >= 0) || (n_igs <= 11))
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);
devprop_add_value(device, "AAPL,ig-platform-id", ivy_bridge_ig_vals[n_igs], 4);
}
else
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 11.\n");
}
}
else
{
uint32_t ig_platform_id;
uint32_t ram = (((getVBEVideoRam() + 512) / 1024) + 512) / 1024;
switch (ram)
{
case 96:
ig_platform_id = 0x01660000; // 96mb Mobile
break;
case 64:
ig_platform_id = 0x01660009; // 64mb Mobile
break;
case 32:
ig_platform_id = 0x01620005; // 32mb Desktop
break;
default:
printf("Please specify 96, 64, or 32MB RAM for the HD4000 in the bios.\n"
"The selected %dMB RAM configuration is not supported for the HD4000.\n", ram);
pause();
return false; // Exit early before the AAPL,ig-platform-id property is set.
break;
}
devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);
}
devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
break;
/* Haswell */
/* HD Graphics 5000, HD Graphics 5000 Mobile, HD Graphics P5000, HD Graphics 4600, HD Graphics 4600 Mobile */
//case 0x80860090:
//case 0x80860091:
//case 0x80860092:
case GMA_HASWELL_D_GT1: // 0402
case GMA_HASWELL_M_GT1: // 0406
case GMA_HASWELL_S_GT1: // 040a
case GMA_HASWELL_D_GT2: // 0412
case GMA_HASWELL_M_GT2: // 0416
case GMA_HASWELL_S_GT2: // 041a
case GMA_HASWELL_E_GT1: // 040e
case GMA_HASWELL_E_GT2: // 041e
case GMA_HASWELL_E_GT3: // 042e
case GMA_HASWELL_D_GT3: // 0422
case GMA_HASWELL_M_GT3: // 0426
case GMA_HASWELL_S_GT3: // 042a
case GMA_HASWELL_ULT_M_GT1: // 0a06
case GMA_HASWELL_ULT_E_GT1: // 0a0e
case GMA_HASWELL_ULT_M_GT2: // 0a16
case GMA_HASWELL_ULT_E_GT2: // 0a1e
case GMA_HASWELL_ULT_D_GT3: // 0a22
case GMA_HASWELL_ULT_M_GT3: // 0a26
case GMA_HASWELL_ULT_S_GT3: // 0a2a
case GMA_HASWELL_ULT_E_GT3: // 0a2e
case GMA_HASWELL_SDV_D_GT1_IG: // 0c02
case GMA_HASWELL_SDV_M_GT1_IG: // 0c06
case GMA_HASWELL_SDV_D_GT2_IG: // 0c12
case GMA_HASWELL_SDV_M_GT2_IG: // 0c16
case GMA_HASWELL_SDV_D_GT2_PLUS_IG: // 0c22
case GMA_HASWELL_SDV_M_GT2_PLUS_IG: // 0c26
case GMA_HASWELL_CRW_D_GT1: // 0d02
case GMA_HASWELL_CRW_D_GT2: // 0d12
case GMA_HASWELL_CRW_D_GT3: // 0d22
case GMA_HASWELL_CRW_M_GT1: // 0d06
case GMA_HASWELL_CRW_M_GT2: // 0d16
case GMA_HASWELL_CRW_M_GT3: // 0d26
case GMA_HASWELL_CRW_S_GT1: // 0d0a
case GMA_HASWELL_CRW_S_GT2: // 0d1a
case GMA_HASWELL_CRW_S_GT3: // 0d2a
case GMA_HASWELL_CRW_B_GT1: // 0d0b
case GMA_HASWELL_CRW_B_GT2: // 0d1b
case GMA_HASWELL_CRW_B_GT3: // 0d2b
case GMA_HASWELL_CRW_E_GT1: // 0d0e
case GMA_HASWELL_CRW_E_GT2: // 0d1e
case GMA_HASWELL_CRW_E_GT3: // 0d2e
case GMA_HASWELL_CRW_M_GT2_PLUS_IG: // 0d36
if (getValueForKey(kAAPLCustomIG, &value, &len, &bootInfo->chameleonConfig) && len == AAPL_LEN_HSW * 2)
{
uint8_t new_aapl0[AAPL_LEN_HSW];
if (hex2bin(value, new_aapl0, AAPL_LEN_HSW) == 0)
{
memcpy(default_aapl_haswell, new_aapl0, AAPL_LEN_HSW);
verbose("Using user supplied AAPL,ig-platform-id\n");
verbose("AAPL,ig-platform-id: %02x%02x%02x%02x\n",
default_aapl_haswell[0], default_aapl_haswell[1], default_aapl_haswell[2], default_aapl_haswell[3]);
}
devprop_add_value(device, "AAPL,ig-platform-id", default_aapl_haswell, AAPL_LEN_HSW);
}
else if (getIntForKey(kIntelAzulFB, &n_igs, &bootInfo->chameleonConfig))
{
if ((n_igs >= 0) || (n_igs <= 15))
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with value %d\n", n_igs);
devprop_add_value(device, "AAPL,ig-platform-id", haswell_ig_vals[n_igs], 4);
}
else
{
verbose("AAPL,ig-platform-id was set in org.chameleon.Boot.plist with bad value please choose a number between 0 and 15.\n");
}
}
else
{
uint32_t ig_platform_id = 0x0000260c; // set the default platform ig
devprop_add_value(device, "AAPL,ig-platform-id", (uint8_t *)&ig_platform_id, 4);
}
devprop_add_value(device, "AAPL00,DualLink", HD4000_vals[10], 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", 10);
break;
default:
break;
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if (!stringdata)
{
printf("No stringdata.\n");
pause();
return false;
}
verbose("---------------------------------------------\n");
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
bool getSMBOemProcessorBusSpeed(returnType *value)
{
if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel
switch (Platform.CPU.Family) {
case 0x06:
{
switch (Platform.CPU.Model) {
case CPU_MODEL_PENTIUM_M:
case CPU_MODEL_DOTHAN: // Intel Pentium M
case CPU_MODEL_YONAH: // Intel Mobile Core Solo, Duo
case CPU_MODEL_MEROM: // Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx
case CPU_MODEL_PENRYN: // Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx
case CPU_MODEL_ATOM: // Intel Atom (45nm)
return false;
case 0x19:
case CPU_MODEL_NEHALEM: // Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)
case CPU_MODEL_FIELDS: // Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)
case CPU_MODEL_DALES:
case CPU_MODEL_DALES_32NM: // Intel Core i3, i5 LGA1156 (32nm)
case CPU_MODEL_WESTMERE: // Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core
case CPU_MODEL_NEHALEM_EX: // Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x
case CPU_MODEL_WESTMERE_EX: // Intel Xeon E7
// case CPU_MODEL_SANDYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (32nm) // MacMan removed not valid for this CPU
// case CPU_MODEL_IVYBRIDGE: // Intel Core i3, i5, i7 LGA1155 (22nm) // MacMan removed not valid for this CPU
// case CPU_MODEL_IVYBRIDGE_XEON: // MacMan moved
// case CPU_MODEL_HASWELL: // MacMan removed not valid for this CPU
// case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)// MacMan moved
{
// thanks to dgobe for i3/i5/i7 bus speed detection
int nhm_bus = 0x3F;
static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};
unsigned long did, vid;
unsigned int i;
// Nehalem supports Scrubbing
// First, locate the PCI bus where the MCH is located
for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {
vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);
did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);
vid &= 0xFFFF;
did &= 0xFF00;
if(vid == 0x8086 && did >= 0x2C00) {
nhm_bus = possible_nhm_bus[i];
}
}
unsigned long qpimult, qpibusspeed;
qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);
qpimult &= 0x7F;
DBG("qpimult %d\n", qpimult);
qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));
// Rek: rounding decimals to match original mac profile info
if (qpibusspeed%100 != 0) {
qpibusspeed = ((qpibusspeed+50)/100)*100;
}
DBG("qpibusspeed %d\n", qpibusspeed);
value->word = qpibusspeed;
return true;
}
// MacMan the following CPUs have fixed DMI2 speeds
case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm)
case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)
case CPU_MODEL_HASWELL_SVR: // Intel Core i7, Xeon E5 LGA2011v3
{
unsigned long dmi2speed;
dmi2speed = 5000;
DBG("dmi2speed %d\n", dmi2speed);
value->word = dmi2speed;
return true;
}
default:
break; //Unsupported CPU type
}
}
default:
break;
}
}
return false;
}
static uint32_t camkes_pci_read32(void *cookie, vmm_pci_address_t addr, unsigned int offset) {
return pci_config_read32(addr.bus, addr.dev, addr.fun, offset);
}
bool setup_gma_devprop(pci_dt_t *gma_dev)
{
char *devicepath;
volatile uint8_t *regs;
uint32_t bar[7];
char *model;
uint8_t BuiltIn = 0x00;
uint8_t ClassFix[4] = { 0x00, 0x00, 0x03, 0x00 };
devicepath = get_pci_dev_path(gma_dev);
bar[0] = pci_config_read32(gma_dev->dev.addr, 0x10);
regs = (uint8_t *) (bar[0] & ~0x0f);
model = get_gma_model((gma_dev->vendor_id << 16) | gma_dev->device_id);
verbose("Intel %s [%04x:%04x] :: %s\n",
model, gma_dev->vendor_id, gma_dev->device_id, devicepath);
if (!string)
string = devprop_create_string();
struct DevPropDevice *device = malloc(sizeof(struct DevPropDevice));
device = devprop_add_device(string, devicepath);
if (!device)
{
printf("Failed initializing dev-prop string dev-entry, press any key...\n");
getchar();
return false;
}
devprop_add_value(device, "model", (uint8_t*)model, (strlen(model) + 1));
devprop_add_value(device, "device_type", (uint8_t*)"display", 8);
if ((model == (char *)"Mobile GMA950")
|| (model == (char *)"Mobile GMA3150"))
{
devprop_add_value(device, "AAPL,HasPanel", reg_TRUE, 4);
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if ((model == (char *)"Desktop GMA950")
|| (model == (char *)"Desktop GMA3150"))
{
BuiltIn = 0x01;
devprop_add_value(device, "built-in", &BuiltIn, 1);
devprop_add_value(device, "class-code", ClassFix, 4);
}
else if (model == (char *)"GMAX3100")
{
devprop_add_value(device, "AAPL,HasPanel", GMAX3100_vals[0], 4);
devprop_add_value(device, "AAPL,SelfRefreshSupported", GMAX3100_vals[1], 4);
devprop_add_value(device, "AAPL,aux-power-connected", GMAX3100_vals[2], 4);
devprop_add_value(device, "AAPL,backlight-control", GMAX3100_vals[3], 4);
devprop_add_value(device, "AAPL00,blackscreen-preferences", GMAX3100_vals[4], 4);
devprop_add_value(device, "AAPL01,BacklightIntensity", GMAX3100_vals[5], 4);
devprop_add_value(device, "AAPL01,blackscreen-preferences", GMAX3100_vals[6], 4);
devprop_add_value(device, "AAPL01,DataJustify", GMAX3100_vals[7], 4);
devprop_add_value(device, "AAPL01,Depth", GMAX3100_vals[8], 4);
devprop_add_value(device, "AAPL01,Dither", GMAX3100_vals[9], 4);
devprop_add_value(device, "AAPL01,DualLink", GMAX3100_vals[10], 4);
devprop_add_value(device, "AAPL01,Height", GMAX3100_vals[11], 4);
devprop_add_value(device, "AAPL01,Interlace", GMAX3100_vals[12], 4);
devprop_add_value(device, "AAPL01,Inverter", GMAX3100_vals[13], 4);
devprop_add_value(device, "AAPL01,InverterCurrent", GMAX3100_vals[14], 4);
devprop_add_value(device, "AAPL01,InverterCurrency", GMAX3100_vals[15], 4);
devprop_add_value(device, "AAPL01,LinkFormat", GMAX3100_vals[16], 4);
devprop_add_value(device, "AAPL01,LinkType", GMAX3100_vals[17], 4);
devprop_add_value(device, "AAPL01,Pipe", GMAX3100_vals[18], 4);
devprop_add_value(device, "AAPL01,PixelFormat", GMAX3100_vals[19], 4);
devprop_add_value(device, "AAPL01,Refresh", GMAX3100_vals[20], 4);
devprop_add_value(device, "AAPL01,Stretch", GMAX3100_vals[21], 4);
devprop_add_value(device, "class-code", ClassFix, 4);
}
stringdata = malloc(sizeof(uint8_t) * string->length);
if (!stringdata)
{
printf("no stringdata press a key...\n");
getchar();
return false;
}
memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
stringlength = string->length;
return true;
}
