int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
struct memac_mdio_info tg_memac_mdio_info;
unsigned int i;
unsigned int serdes1_prtcl, serdes2_prtcl;
int qsgmii;
struct mii_dev *bus;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
if (!serdes1_prtcl) {
printf("SERDES1 is not enabled\n");
return 0;
}
serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
if (!serdes2_prtcl) {
printf("SERDES2 is not enabled\n");
return 0;
}
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
printf("Initializing Fman\n");
initialize_lane_to_slot();
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
tg_memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_memac_mdio_init(bis, &tg_memac_mdio_info);
/*
* Program the two on board DTSEC PHY addresses assuming that they are
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_ARCH_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
break;
case 0x48:
case 0x49:
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
case 0xb1:
case 0xb2:
case 0x8c:
case 0x8d:
debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
/*
* XFI does not need a PHY to work, but to make U-Boot
* happy, assign a fake PHY address for a XFI port.
*/
fm_info_set_phy_address(FM1_10GEC1, 0);
fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
/*set PHY address for QSGMII Riser Card on slot2*/
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
if (qsgmii) {
switch (serdes2_prtcl) {
case 0xb2:
case 0x8d:
fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
break;
default:
break;
}
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
int idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name
(DEFAULT_FM_TGEC_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk();
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
/*
* Program on board RGMII PHY addresses. If the SGMII Riser
* card used, we'll override the PHY address later. For any DTSEC that
* is RGMII, we'll also override its PHY address later. We assume that
* DTSEC4 and DTSEC5 are used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
break;
case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_RGMII:
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
t1040_handle_phy_interface_rgmii(i);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
printf("Initializing Fman\n");
initialize_lane_to_slot();
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
memset(mdio_mux, 0, sizeof(mdio_mux));
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/* Register the three virtual MDIO front-ends */
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
"SUPER_HYDRA_RGMII_MDIO");
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
"SUPER_HYDRA_FM1_SGMII_MDIO");
super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME,
"SUPER_HYDRA_FM2_SGMII_MDIO");
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
"SUPER_HYDRA_FM1_TGEC_MDIO");
super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME,
"SUPER_HYDRA_FM2_TGEC_MDIO");
/*
* Program the DTSEC PHY addresses assuming that they are all SGMII.
* For any DTSEC that's RGMII, we'll override its PHY address later.
* We assume that DTSEC5 is only used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
#if (CONFIG_SYS_NUM_FMAN == 2)
fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
#endif
switch (srds_prtcl) {
case 0:
case 3:
case 4:
case 6:
case 0x11:
case 0x2a:
case 0x34:
case 0x36:
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
break;
case 1:
case 2:
case 5:
case 7:
case 0x35:
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
break;
default:
printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
switch (slot) {
case 1:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
BRDCFG1_EMI1_EN;
break;
case 2:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
BRDCFG1_EMI1_EN;
break;
case 3:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
BRDCFG1_EMI1_EN;
break;
case 5:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
BRDCFG1_EMI1_EN;
break;
case 6:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
BRDCFG1_EMI1_EN;
break;
case 7:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
BRDCFG1_EMI1_EN;
break;
};
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
* second on-board RGMII port. The other DTSECs cannot
* be routed to RGMII.
*/
debug("FM1@DTSEC%u is RGMII at address %u\n",
idx + 1, 0);
fm_info_set_phy_address(i, 0);
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
BRDCFG1_EMI1_EN;
super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
/*
* For 10G, we only support one XAUI card per Fman. If present, then we
* force its routing and never touch those bits again, which removes the
* need for Linux to do any muxing. This works because of the way
* BRDCFG1 is defined, but it's a bit hackish.
*
* The PHY address for the XAUI card depends on which slot it's in. The
* macros we use imply that the PHY address is based on which FM, but
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
* check the actual slot and just use the macros as-is, even though
* the P3041 and P5020 only have one Fman.
*/
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2;
super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
}
fm_info_set_mdio(FM1_10GEC1,
miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO"));
#if (CONFIG_SYS_NUM_FMAN == 2)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
int idx = i - FM2_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
debug("FM2@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
switch (slot) {
case 1:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
BRDCFG1_EMI1_EN;
break;
case 2:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
BRDCFG1_EMI1_EN;
break;
case 3:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 |
BRDCFG1_EMI1_EN;
break;
case 5:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
BRDCFG1_EMI1_EN;
break;
case 6:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
BRDCFG1_EMI1_EN;
break;
case 7:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
BRDCFG1_EMI1_EN;
break;
};
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* FM1 DTSEC5 is routed via EC1 to the first on-board
* RGMII port. FM2 DTSEC5 is routed via EC2 to the
* second on-board RGMII port. The other DTSECs cannot
* be routed to RGMII.
*/
debug("FM2@DTSEC%u is RGMII at address %u\n",
idx + 1, 1);
fm_info_set_phy_address(i, 1);
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
BRDCFG1_EMI1_EN;
super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman2: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
/*
* For 10G, we only support one XAUI card per Fman. If present, then we
* force its routing and never touch those bits again, which removes the
* need for Linux to do any muxing. This works because of the way
* BRDCFG1 is defined, but it's a bit hackish.
*
* The PHY address for the XAUI card depends on which slot it's in. The
* macros we use imply that the PHY address is based on which FM, but
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
* check the actual slot and just use the macros as-is, even though
* the P3041 and P5020 only have one Fman.
*/
lane = serdes_get_first_lane(XAUI_FM2);
if (lane >= 0) {
debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]);
mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK;
mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1;
super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
}
fm_info_set_mdio(FM2_10GEC1,
miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO"));
#endif
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Initialize TSECs first */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x66:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
int phy_addr = 0;
#ifdef CONFIG_VSC9953
phy_interface_t phy_int;
struct mii_dev *bus;
#endif
printf("Initializing Fman\n");
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
/*
* Program on board RGMII, SGMII PHY addresses.
*/
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1040D4RDB)
case PHY_INTERFACE_MODE_SGMII:
/* T1040RDB & T1040D4RDB only supports SGMII on
* DTSEC3
*/
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_T1042RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
fm_info_set_phy_address(i, 0);
/* T1042RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_T1042D4RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2
* & DTSEC3
*/
if (FM1_DTSEC1 == i)
phy_addr = CONFIG_SYS_SGMII1_PHY_ADDR;
if (FM1_DTSEC2 == i)
phy_addr = CONFIG_SYS_SGMII2_PHY_ADDR;
if (FM1_DTSEC3 == i)
phy_addr = CONFIG_SYS_SGMII3_PHY_ADDR;
fm_info_set_phy_address(i, phy_addr);
break;
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
if (FM1_DTSEC5 == i)
phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
fm_info_set_phy_address(i, phy_addr);
break;
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, 0);
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||
fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NONE)
fm_info_set_mdio(i, NULL);
else
fm_info_set_mdio(i,
miiphy_get_dev_by_name(
DEFAULT_FM_MDIO_NAME));
}
#ifdef CONFIG_VSC9953
/* SerDes configured for QSGMII */
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A) >= 0) {
for (i = 0; i < 4; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR + i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
vsc9953_port_enable(i);
}
}
if (serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B) >= 0) {
for (i = 4; i < 8; i++) {
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR + i - 4;
phy_int = PHY_INTERFACE_MODE_QSGMII;
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
vsc9953_port_enable(i);
}
}
/* Connect DTSEC1 to L2 switch if it doesn't have a PHY */
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1) < 0)
vsc9953_port_enable(8);
/* Connect DTSEC2 to L2 switch if it doesn't have a PHY */
if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
CONFIG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) |
(0x80000000));
vsc9953_port_enable(9);
}
#endif
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
/* Initialize built-in FEC first */
cpu_eth_init(bis);
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
u8 brdcfg12;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
srds_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x3333:
/* SGMII on slot 1, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
case 0x1333:
case 0x2333:
/* SGMII on slot 1, MAC 10 */
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
case 0x1133:
case 0x2233:
/* SGMII on slot 1, MAC 5/6 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x1040:
case 0x2040:
/* QSGMII on lane B, MAC 6/5/10/1 */
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT1_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT2_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC10,
QSGMII_CARD_PORT3_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT4_PHY_ADDR_S2);
break;
case 0x3363:
/* SGMII on slot 1, MAC 9/10 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
case 0x1163:
case 0x2263:
case 0x2223:
/* SGMII on slot 1, MAC 6 */
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
default:
printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
srds_s1);
break;
}
if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
/* SGMII on slot 4, MAC 2 */
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
if (i == FM1_DTSEC5) {
/* route lane 2 to slot1 so to have
* one sgmii riser card supports
* MAC5 and MAC6.
*/
brdcfg12 = QIXIS_READ(brdcfg[12]);
QIXIS_WRITE(brdcfg[12],
brdcfg12 | 0x80);
}
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else {
/* clear the bit 7 to route lane B on slot2. */
brdcfg12 = QIXIS_READ(brdcfg[12]);
QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
lane_to_slot[lane] = 2;
}
if (i == FM1_DTSEC2)
lane = 5;
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
default:
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_TXID:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4)
mdio_mux[i] = EMI1_RGMII2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t4240qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
t4240qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
initialize_qsgmiiphy_fix();
switch (srds_prtcl_s1) {
case 1:
case 2:
case 4:
/* XAUI/HiGig in Slot1 and Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
break;
case 28:
case 36:
/* SGMII in Slot1 and Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][3]);
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
}
break;
case 38:
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][2]);
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][3]);
}
break;
case 40:
case 46:
case 48:
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
if ((srds_prtcl_s2 != 56) && (srds_prtcl_s2 != 57)) {
fm_info_set_phy_address(FM1_DTSEC10,
slot_qsgmii_phyaddr[1][2]);
fm_info_set_phy_address(FM1_DTSEC9,
slot_qsgmii_phyaddr[1][3]);
}
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
fm_info_set_phy_address(FM1_DTSEC3, slot_qsgmii_phyaddr[2][2]);
fm_info_set_phy_address(FM1_DTSEC4, slot_qsgmii_phyaddr[2][3]);
break;
default:
puts("Invalid SerDes1 protocol for T4240QDS\n");
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_QSGMII) {
if (idx <= 3)
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
else
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_B);
if (lane < 0)
break;
slot = lane_to_slot_fsm1[lane];
debug("FM1@DTSEC%u expects QSGMII in slot %u\n",
idx + 1, slot);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm1[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
}
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
/* FM1 DTSEC5 routes to RGMII with EC2 */
debug("FM1@DTSEC%u is RGMII at address %u\n",
idx + 1, 2);
if (i == FM1_DTSEC5)
fm_info_set_phy_address(i, 2);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
XAUI_FM1_MAC9 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm1[lane];
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
switch (srds_prtcl_s2) {
case 1:
case 2:
case 4:
/* XAUI/HiGig in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
break;
case 7:
case 13:
case 14:
case 16:
case 22:
case 23:
case 25:
case 26:
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 28:
case 36:
/* SGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
case 38:
/* QSGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
break;
case 40:
case 46:
case 48:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC6, slot_qsgmii_phyaddr[3][1]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
/* QSGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 50:
case 52:
case 54:
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
case 56:
case 57:
/* XFI in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC2, slot_qsgmii_phyaddr[4][1]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
default:
puts("Invalid SerDes2 protocol for T4240QDS\n");
break;
}
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
idx = i - FM2_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_QSGMII) {
if (idx <= 3)
lane = serdes_get_first_lane(FSL_SRDS_2,
QSGMII_FM2_A);
else
lane = serdes_get_first_lane(FSL_SRDS_2,
QSGMII_FM2_B);
if (lane < 0)
break;
slot = lane_to_slot_fsm2[lane];
debug("FM2@DTSEC%u expects QSGMII in slot %u\n",
idx + 1, slot);
} else {
lane = serdes_get_first_lane(FSL_SRDS_2,
SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm2[lane];
debug("FM2@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
}
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* If DTSEC5 is RGMII, then it's routed via via EC1 to
* the first on-board RGMII port. If DTSEC6 is RGMII,
* then it's routed via via EC2 to the second on-board
* RGMII port.
*/
debug("FM2@DTSEC%u is RGMII at address %u\n",
idx + 1, i == FM2_DTSEC5 ? 1 : 2);
fm_info_set_phy_address(i, i == FM2_DTSEC5 ? 1 : 2);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
idx = i - FM2_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(FSL_SRDS_2,
XAUI_FM2_MAC9 + idx);
if (lane < 0)
break;
slot = lane_to_slot_fsm2[lane];
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
#endif /* CONFIG_SYS_NUM_FMAN */
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
#if defined(CONFIG_T2080QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
#endif
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
#if defined(CONFIG_T2081QDS)
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
#endif
t208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
else
fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x1b:
case 0x1c:
case 0x95:
case 0xa2:
case 0x94:
/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
/* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x50:
case 0x51:
case 0x5e:
case 0x5f:
case 0x64:
case 0x65:
/* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
/* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x66:
case 0x67:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks
* the XAUI card is used for the XFI MAC, which will cause
* error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
break;
case 0x6a:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
/* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
case 0x6c:
case 0x6d:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
/* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x70:
case 0x71:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
/* SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
case 0xa6:
case 0x8e:
case 0x8f:
case 0x82:
case 0x83:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
/* SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
case 0xa4:
case 0x96:
case 0x8a:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
#if defined(CONFIG_T2080QDS)
case 0xd9:
case 0xd3:
case 0xcb:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
/* SGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
break;
#elif defined(CONFIG_T2081QDS)
case 0xca:
case 0xcb:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);
/* SGMII in Slot5 */
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
/* SGMII in Slot6 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
/* SGMII in Slot7 */
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
break;
#endif
case 0xf2:
/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
default:
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
#if defined(CONFIG_T2081QDS)
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 6:
mdio_mux[i] = EMI1_SLOT6;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 7:
mdio_mux[i] = EMI1_SLOT7;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
#endif
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4 || FM1_DTSEC10)
mdio_mux[i] = EMI1_RGMII2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
if (srds_s1 == 0x51) {
lane = serdes_get_first_lane(FSL_SRDS_1,
XAUI_FM1_MAC9 + idx);
} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {
lane = serdes_get_first_lane(FSL_SRDS_1,
HIGIG_FM1_MAC9 + idx);
} else {
if (i == FM1_10GEC1 || i == FM1_10GEC2)
lane = serdes_get_first_lane(FSL_SRDS_1,
XFI_FM1_MAC9 + idx);
else
lane = serdes_get_first_lane(FSL_SRDS_1,
XFI_FM1_MAC1 + idx);
}
if (lane < 0)
break;
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
(srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
(srds_s1 == 0x71)) {
/* As XFI is in cage intead of a slot, so
* ensure doesn't disable the corresponding port
*/
break;
}
slot = lane_to_slot[lane];
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct memac_mdio_controller *reg;
u32 srds_s1, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
FSL_CHASSIS3_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS3_SRDS1_PRTCL_SHIFT;
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the EMI 2 */
fm_memac_mdio_init(bis, &mdio_info);
switch (srds_s1) {
case 0x1D:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC error.
*/
wriop_set_phy_address(WRIOP1_DPMAC1, 0x0a);
wriop_set_phy_address(WRIOP1_DPMAC2, AQ_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC3, QSGMII1_PORT1_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC4, QSGMII1_PORT2_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC5, QSGMII1_PORT3_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC6, QSGMII1_PORT4_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC7, QSGMII2_PORT1_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC8, QSGMII2_PORT2_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC9, QSGMII2_PORT3_PHY_ADDR);
wriop_set_phy_address(WRIOP1_DPMAC10, QSGMII2_PORT4_PHY_ADDR);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS1088ARDB\n",
srds_s1);
break;
}
for (i = WRIOP1_DPMAC3; i <= WRIOP1_DPMAC10; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_QSGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
wriop_set_mdio(WRIOP1_DPMAC2, dev);
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Built in FEC comes first */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_VSC7385_ENET
char *tmp;
unsigned int vscfw_addr;
#endif
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
printf("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
#ifdef CONFIG_VSC7385_ENET
/* If a VSC7385 microcode image is present, then upload it. */
tmp = env_get("vscfw_addr");
if (tmp) {
vscfw_addr = simple_strtoul(tmp, NULL, 16);
printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
if (vsc7385_upload_firmware((void *) vscfw_addr,
CONFIG_VSC7385_IMAGE_SIZE))
puts("Failure uploading VSC7385 microcode.\n");
} else
puts("No address specified for VSC7385 microcode.\n");
#endif
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#if defined(CONFIG_UEC_ETH)
/* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
uec_standard_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
int phy_addr = 0;
printf("Initializing Fman\n");
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
/*
* Program on board RGMII, SGMII PHY addresses.
*/
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
#ifdef CONFIG_T1040RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1040RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
#ifdef CONFIG_T1042RDB
case PHY_INTERFACE_MODE_SGMII:
/* T1042RDB doesn't supports SGMII on DTSEC1 & DTSEC2 */
if ((FM1_DTSEC1 == i) || (FM1_DTSEC2 == i))
fm_info_set_phy_address(i, 0);
/* T1042RDB only supports SGMII on DTSEC3 */
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_SGMII1_PHY_ADDR);
break;
#endif
case PHY_INTERFACE_MODE_RGMII:
if (FM1_DTSEC4 == i)
phy_addr = CONFIG_SYS_RGMII1_PHY_ADDR;
if (FM1_DTSEC5 == i)
phy_addr = CONFIG_SYS_RGMII2_PHY_ADDR;
fm_info_set_phy_address(i, phy_addr);
break;
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_phy_address(i, 0);
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
printf("Initializing Fman\n");
initialize_lane_to_slot();
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/*
* Program the three on-board SGMII PHY addresses. If the SGMII Riser
* card used, we'll override the PHY address later. For any DTSEC that
* is RGMII, we'll also override its PHY address later. We assume that
* DTSEC4 and DTSEC5 are used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
if (slot)
fm_info_set_phy_address(i, riser_phy_addr[i]);
break;
case PHY_INTERFACE_MODE_RGMII:
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
break;
}
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
}
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
slot = lane_to_slot[lane];
if (slot)
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
}
fm_info_set_mdio(FM1_10GEC1,
miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
int error;
#ifdef CONFIG_FSL_MC_ENET
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
struct memac_mdio_info *memac_mdio0_info;
struct memac_mdio_info *memac_mdio1_info;
unsigned int i;
char *env_hwconfig;
env_hwconfig = getenv("hwconfig");
initialize_dpmac_to_slot();
memac_mdio0_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
fm_memac_mdio_init(bis, memac_mdio0_info);
memac_mdio1_info = (struct memac_mdio_info *)malloc(
sizeof(struct memac_mdio_info));
memac_mdio1_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO2;
memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */
fm_memac_mdio_init(bis, memac_mdio1_info);
/* Register the muxing front-ends to the MDIO buses */
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
ls2080a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
ls2080a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
ls2080a_handle_phy_interface_xsgmii(i);
break;
default:
break;
if (i == 16)
i = NUM_WRIOP_PORTS;
}
}
error = cpu_eth_init(bis);
if (hwconfig_f("xqsgmii", env_hwconfig)) {
if (serdes1_prtcl == 0x7)
sgmii_configure_repeater(1);
if (serdes2_prtcl == 0x7 || serdes2_prtcl == 0x8 ||
serdes2_prtcl == 0x49)
sgmii_configure_repeater(2);
}
#endif
error = pci_eth_init(bis);
return error;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
int i;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
/* QSGMII on lane B, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);
switch (srds_s1) {
case 0x1455:
break;
default:
printf("Invalid SerDes protocol 0x%x for LS1043ARDB\n",
srds_s1);
break;
}
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);
/* XFI on lane A, MAC 9 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
#ifdef CONFIG_T1024RDB
case 0x95:
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
/* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
#endif
case 0x6a:
case 0x6b:
case 0x77:
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
#ifdef CONFIG_T1023RDB
/* set the on-board 1G SGMII RTL8211F PHY */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
#endif
break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII:
#if defined(CONFIG_T1023RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
#elif defined(CONFIG_T1024RDB)
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
#endif
fm_info_set_mdio(i, dev);
break;
case PHY_INTERFACE_MODE_SGMII_2500:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
/* Initialize TSECs */
cpu_eth_init(bis);
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
cpu_eth_init(bis); /* Built in controller(s) come first */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x2555:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
break;
case 0x4555:
case 0x4558:
/* QSGMII on lane A, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT1_PHY_ADDR_S1);
fm_info_set_phy_address(FM1_DTSEC2,
QSGMII_CARD_PORT2_PHY_ADDR_S1);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT3_PHY_ADDR_S1);
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT4_PHY_ADDR_S1);
break;
case 0x1355:
/* SGMII on lane B, MAC 2*/
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x2355:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
/* SGMII on lane B, MAC 2*/
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x3335:
/* SGMII on lane C, MAC 5 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
case 0x3355:
case 0x3358:
/* SGMII on lane B, MAC 2 */
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
case 0x3555:
case 0x3558:
/* SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x1455:
/* QSGMII on lane B, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT1_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC2,
QSGMII_CARD_PORT2_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT3_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT4_PHY_ADDR_S2);
break;
case 0x2455:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
/* QSGMII on lane B, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT1_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC2,
QSGMII_CARD_PORT2_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT3_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT4_PHY_ADDR_S2);
break;
case 0x2255:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
/* 2.5G SGMII on lane B, MAC 2 */
fm_info_set_phy_address(FM1_DTSEC2, 2);
break;
case 0x3333:
/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC9,
SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
SGMII_CARD_PORT1_PHY_ADDR);
break;
default:
printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
}
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
default:
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4)
mdio_mux[i] = EMI1_RGMII2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0xd5:
case 0xd6:
/* QSGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, 0x8);
fm_info_set_phy_address(FM1_DTSEC2, 0x9);
fm_info_set_phy_address(FM1_DTSEC3, 0xa);
fm_info_set_phy_address(FM1_DTSEC4, 0xb);
break;
case 0x95:
case 0x99:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks the
* XAUI card is used for the XFI MAC, which will cause error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6f:
/* SGMII in Slot3, Slot4, Slot5 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x7f:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
break;
case 0x47:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x77:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
break;
case 0x5a:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6a:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x5b:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6b:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
default:
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
}
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII2;
else if (i == FM1_DTSEC4)
mdio_mux[i] = EMI1_RGMII1;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
XFI_FM1_MAC1 + idx);
if (lane < 0)
break;
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
unsigned int i;
#ifdef CONFIG_VSC9953
int lane;
int phy_addr;
phy_interface_t phy_int;
struct mii_dev *bus;
#endif
printf("Initializing Fman\n");
set_brdcfg9_for_gtx_clk();
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
/*
* Program on board RGMII PHY addresses. If the SGMII Riser
* card used, we'll override the PHY address later. For any DTSEC that
* is RGMII, we'll also override its PHY address later. We assume that
* DTSEC4 and DTSEC5 are used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
fm_info_set_mdio(i, NULL);
break;
case PHY_INTERFACE_MODE_SGMII:
t1040_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_RGMII:
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
t1040_handle_phy_interface_rgmii(i);
break;
default:
break;
}
}
#ifdef CONFIG_VSC9953
for (i = 0; i < VSC9953_MAX_PORTS; i++) {
lane = -1;
phy_addr = 0;
phy_int = PHY_INTERFACE_MODE_NONE;
switch (i) {
case 0:
case 1:
case 2:
case 3:
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
/* PHYs connected over QSGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
i;
phy_int = PHY_INTERFACE_MODE_QSGMII;
break;
}
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_SW1_MAC1 + i);
if (lane < 0)
break;
/* PHYs connected over QSGMII */
if (i != 3 || lane_to_slot[lane] == 7)
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ i;
else
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
phy_int = PHY_INTERFACE_MODE_SGMII;
break;
case 4:
case 5:
case 6:
case 7:
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
/* PHYs connected over QSGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
i - 4;
phy_int = PHY_INTERFACE_MODE_QSGMII;
break;
}
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_SW1_MAC1 + i);
/* PHYs connected over SGMII */
if (lane >= 0) {
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
+ i - 3;
phy_int = PHY_INTERFACE_MODE_SGMII;
}
break;
case 8:
if (serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1) < 0)
/* FM1@DTSEC1 is connected to SW1@PORT8 */
vsc9953_port_enable(i);
break;
case 9:
if (serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC2) < 0) {
/* Enable L2 On MAC2 using SCFG */
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
CONFIG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr,
in_be32(&scfg->esgmiiselcr) |
(0x80000000));
vsc9953_port_enable(i);
}
break;
}
if (lane >= 0) {
bus = mii_dev_for_muxval(lane_to_slot[lane]);
vsc9953_port_info_set_mdio(i, bus);
vsc9953_port_enable(i);
}
vsc9953_port_info_set_phy_address(i, phy_addr);
vsc9953_port_info_set_phy_int(i, phy_int);
}
#endif
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
struct mii_dev *bus;
printf("Initializing Fman\n");
initialize_lane_to_slot();
/* We want to use the PIXIS to configure MUX routing, not GPIOs. */
setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
memset(mdio_mux, 0, sizeof(mdio_mux));
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/* Register the three virtual MDIO front-ends */
hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
/*
* Program the DTSEC PHY addresses assuming that they are all SGMII.
* For any DTSEC that's RGMII, we'll override its PHY address later.
* We assume that DTSEC5 is only used for RGMII.
*/
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
switch (slot) {
case 1:
/* Always DTSEC5 on Bank 3 */
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
BRDCFG1_EMI1_EN;
break;
case 2:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
BRDCFG1_EMI1_EN;
break;
case 5:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
BRDCFG1_EMI1_EN;
break;
case 6:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
BRDCFG1_EMI1_EN;
break;
case 7:
mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
BRDCFG1_EMI1_EN;
break;
};
hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_RGMII:
/*
* If DTSEC4 is RGMII, then it's routed via via EC1 to
* the first on-board RGMII port. If DTSEC5 is RGMII,
* then it's routed via via EC2 to the second on-board
* RGMII port. The other DTSECs cannot be routed to
* RGMII.
*/
fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
BRDCFG1_EMI1_EN;
hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
mdio_mux[i].mask, mdio_mux[i].val);
fm_info_set_mdio(i,
miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
/*
* For 10G, we only support one XAUI card per Fman. If present, then we
* force its routing and never touch those bits again, which removes the
* need for Linux to do any muxing. This works because of the way
* BRDCFG1 is defined, but it's a bit hackish.
*
* The PHY address for the XAUI card depends on which slot it's in. The
* macros we use imply that the PHY address is based on which FM, but
* that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
* and FM2 could only use a XAUI in slot 4. On the Hydra board, we
* check the actual slot and just use the macros as-is, even though
* the P3041 and P5020 only have one Fman.
*/
lane = serdes_get_first_lane(XAUI_FM1);
if (lane >= 0) {
slot = lane_to_slot[lane];
if (slot == 1) {
/* XAUI card is in slot 1 */
clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
BRDCFG1_EMI2_SEL_SLOT1);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
} else {
/* XAUI card is in slot 2 */
clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
BRDCFG1_EMI2_SEL_SLOT2);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
}
}
fm_info_set_mdio(FM1_10GEC1,
miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FSL_MC_ENET)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
struct memac_mdio_controller *reg;
srds_s1 = in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the EMI 2 */
fm_memac_mdio_init(bis, &mdio_info);
switch (srds_s1) {
case 0x2A:
wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
srds_s1);
break;
}
for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
interface = wriop_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
wriop_set_mdio(i, dev);
break;
default:
break;
}
}
/* Load CORTINA CS4340 PHY firmware */
load_phy_firmware();
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
#ifdef CONFIG_PHY_AQUANTIA
/*
* Export functions to be used by AQ firmware
* upload application
*/
gd->jt->strcpy = strcpy;
gd->jt->mdelay = mdelay;
gd->jt->mdio_get_current_dev = mdio_get_current_dev;
gd->jt->phy_find_by_mask = phy_find_by_mask;
gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
#endif
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
struct dtsec *tsec = (void *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
int i;
struct fsl_pq_mdio_info dtsec_mdio_info;
struct tgec_mdio_info tgec_mdio_info;
u8 lane_to_slot[] = {
SLOT1, /* 0 - Bank 1:A */
SLOT1, /* 1 - Bank 1:B */
SLOT2, /* 2 - Bank 1:C */
SLOT2, /* 3 - Bank 1:D */
SLOT3, /* 4 - Bank 1:E */
SLOT3, /* 5 - Bank 1:F */
SLOT3, /* 6 - Bank 1:G */
SLOT3, /* 7 - Bank 1:H */
SLOT6, /* 8 - Bank 1:I */
SLOT6, /* 9 - Bank 1:J */
SLOT4, /* 10 - Bank 2:A */
SLOT4, /* 11 - Bank 2:B */
SLOT4, /* 12 - Bank 2:C */
SLOT4, /* 13 - Bank 2:D */
SLOT5, /* 14 - Bank 3:A */
SLOT5, /* 15 - Bank 3:B */
SLOT5, /* 16 - Bank 3:C */
SLOT5, /* 17 - Bank 3:D */
};
/*
* Set TBIPA on FM1@DTSEC1. This is needed for configurations
* where FM1@DTSEC1 isn't used directly, since it provides
* MDIO for other ports.
*/
out_be32(&tsec->tbipa, CONFIG_SYS_TBIPA_VALUE);
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
/* The first 4 GPIOs are outputs to control MDIO bus muxing */
out_be32(&pgpio->gpdir, EMI_MASK);
dtsec_mdio_info.regs =
(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fsl_pq_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_tgec_mdio_init(bis, &tgec_mdio_info);
/* Register the 6 muxing front-ends to the MDIO buses */
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII);
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
p4080ds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT4);
p4080ds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2_SLOT5);
fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
#if (CONFIG_SYS_NUM_FMAN == 2)
fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC3_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC4_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
#endif
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
fm_info_set_phy_address(i, 0);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
int idx = i - FM1_10GEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(XAUI_FM1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
int idx = i - FM2_DTSEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
case PHY_INTERFACE_MODE_RGMII:
fm_info_set_phy_address(i, 0);
mdio_mux[i] = EMI1_RGMII;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
int idx = i - FM2_10GEC1, lane, slot;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(XAUI_FM2 + idx);
if (lane < 0)
break;
slot = lane_to_slot[lane];
switch (slot) {
case SLOT4:
mdio_mux[i] = EMI2_SLOT4;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
case SLOT5:
mdio_mux[i] = EMI2_SLOT5;
fm_info_set_mdio(i,
mii_dev_for_muxval(mdio_mux[i]));
break;
};
break;
default:
break;
}
}
#endif
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM2_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);
fm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);
} else {
puts("Invalid SerDes1 protocol for T4240RDB\n");
}
fm_disable_port(FM1_DTSEC5);
fm_disable_port(FM1_DTSEC6);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
#if (CONFIG_SYS_NUM_FMAN == 2)
if ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {
/* SGMII && XFI */
fm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);
fm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);
fm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);
fm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);
} else {
puts("Invalid SerDes2 protocol for T4240RDB\n");
}
fm_disable_port(FM2_DTSEC5);
fm_disable_port(FM2_DTSEC6);
for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM2_10GEC1; i < FM2_10GEC1 + CONFIG_SYS_NUM_FM2_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
#endif /* CONFIG_SYS_NUM_FMAN */
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}