void scsi_init(void)
{
/*
* Find a device from the list, this driver will support a single
* controller.
*/
#ifdef CONFIG_SCSI_6820
board_ahci_init();
#endif
#if defined CONFIG_SCSI_MV94XX
int busdevfunc;
if ((busdevfunc = pci_find_devices (mv94xx_pci_ids, 0)) < 0) {
printf("MV94XX controller not present\n");
return;
}
if (scsi_curr_dev == -1)
scsi_low_level_init(busdevfunc);
else
scsi_bus_reset(); /*mult-time "scsi init", no need re-assign resource"*/
#else
int i, busdevfunc, index = 0;
for (;;) {
busdevfunc = pci_find_devices(scsi_device_list, index);
if (busdevfunc == -1) {
if (index == 0) {
printf("Error: SCSI Controller(s) ");
for (i = 0; i < ARRAY_SIZE(scsi_device_list) - 1; i++) {
printf("%04X:%04X ",
scsi_device_list[i].vendor,
scsi_device_list[i].device);
}
printf("not found\n");
}
break;
}
#ifdef DEBUG
else {
printf("SCSI Controller found (%d:%d:%d)\n",
(busdevfunc >> 16) & 0xFF,
(busdevfunc >> 11) & 0x1F,
(busdevfunc >> 8) & 0x7);
}
#endif
scsi_low_level_init(busdevfunc);
index++;
}
#endif
scsi_scan(1);
}
unsigned int pci_video_init(void)
{
GraphicDevice *pGD = (GraphicDevice *)&mb862xx;
pci_dev_t devbusfn;
if ((devbusfn = pci_find_devices(supported, 0)) < 0)
{
printf ("PCI video controller not found!\n");
return 0;
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pGD->frameAdrs);
pGD->frameAdrs = pci_mem_to_phys (devbusfn, pGD->frameAdrs);
if (pGD->frameAdrs == 0) {
printf ("PCI config: failed to get base address\n");
return 0;
}
pGD->pciBase = pGD->frameAdrs;
/* Setup clocks and memory mode for Coral-P Eval. Board */
HOST_WR_REG (0x0038, 0x00090000);
udelay (200);
HOST_WR_REG (0xfffc, 0x11d7fa13);
udelay (100);
return pGD->frameAdrs;
}
pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
{
static struct pci_device_id ids[2] = {{}, {0, 0}};
ids[0].vendor = vendor;
ids[0].device = device;
return pci_find_devices(ids, index);
}
int rtl8169_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
unsigned int region;
u16 device;
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_word(devno, PCI_DEVICE_ID, &device);
switch (device) {
case 0x8168:
region = 2;
break;
default:
region = 1;
break;
}
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8169\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
eth_register (dev);
rtl_init(dev, bis);
card_number++;
}
return card_number;
}
int pch_gbe_register(bd_t *bis)
{
struct eth_device *dev;
struct pch_gbe_priv *priv;
pci_dev_t devno;
u32 iobase;
devno = pci_find_devices(supported, 0);
if (devno == -1)
return -ENODEV;
dev = (struct eth_device *)malloc(sizeof(*dev));
if (!dev)
return -ENOMEM;
memset(dev, 0, sizeof(*dev));
/*
* The priv structure contains the descriptors and frame buffers which
* need a strict buswidth alignment (64 bytes)
*/
priv = (struct pch_gbe_priv *)memalign(PCH_GBE_ALIGN_SIZE,
sizeof(*priv));
if (!priv) {
free(dev);
return -ENOMEM;
}
memset(priv, 0, sizeof(*priv));
dev->priv = priv;
priv->dev = dev;
priv->bdf = devno;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
iobase = pci_mem_to_phys(devno, iobase);
dev->iobase = iobase;
priv->mac_regs = (struct pch_gbe_regs *)iobase;
sprintf(dev->name, "pch_gbe.%x", iobase);
/* Read MAC address from SROM and initialize dev->enetaddr with it */
pch_gbe_mac_read(priv->mac_regs, dev->enetaddr);
dev->init = pch_gbe_init;
dev->halt = pch_gbe_halt;
dev->send = pch_gbe_send;
dev->recv = pch_gbe_recv;
eth_register(dev);
priv->interface = PHY_INTERFACE_MODE_RGMII;
pch_gbe_mdio_init(dev->name, priv->mac_regs);
priv->bus = miiphy_get_dev_by_name(dev->name);
return pch_gbe_phy_init(dev);
}
int i2155x_init(void)
{
pci_dev_t devno;
u32 val;
int i;
/*
* Find the Intel bridge.
*/
if ((devno = pci_find_devices(i2155x_ids, 0)) < 0) {
printf("Error: Intel bridge 2155x not found!\n");
return -1;
}
i2155x.devno = devno;
/*
* Get auto-configured base address for CSR access.
*/
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &val);
if (val & PCI_BASE_ADDRESS_SPACE_IO) {
val &= PCI_BASE_ADDRESS_IO_MASK;
i2155x.csr = (volatile u32 *)(_IO_BASE + val);
} else {
val &= PCI_BASE_ADDRESS_MEM_MASK;
i2155x.csr = (volatile u32 *)val;
}
/*
* Translate downstream memory 2 (bar3) to base of shared memory.
*/
i2155x_set_bar_base(3, PN62_SMEM_DEFAULT);
/*
* Enable memory space, I/O space and bus master bits
* in both Primary and Secondary command registers.
*/
val = PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER|PCI_COMMAND_IO;
pci_write_config_word(devno, 0x44, val);
pci_write_config_word(devno, 0x04, val);
/*
* Clear scratchpad registers.
*/
for (i = 0; i < (I2155X_SCRAPAD_MAX - 1); i++) {
i2155x_write_scrapad(i, 0x0);
}
/*
* Set interrupt line for Linux.
*/
pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 3);
return 0;
}
static u32 probe_pci_video(void)
{
pci_dev_t devbusfn;
if ((devbusfn = pci_find_devices(supported, 0) != -1)) {
u32 old;
u32 addr;
/* PCI video device detected */
printf("Found PCI VGA device at %02x.%02x.%x\n",
PCI_BUS(devbusfn), PCI_DEV(devbusfn), PCI_FUNC(devbusfn));
/* Enable I/O decoding as well, PCI viudeo boards
* support I/O accesses, but they provide no
* bar register for this since the ports are fixed.
*/
pci_write_config_word(devbusfn, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
/* Test the ROM decoder, do the device support a rom? */
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
if (!addr) {
printf("PCI VGA have no ROM?\n");
return 0;
}
/* device have a rom */
if (pci_shadow_rom(devbusfn, (void*)0xc0000)) {
printf("Shadowing of PCI VGA BIOS failed\n");
return 0;
}
/* Now enable lagacy VGA port access */
if (pci_enable_legacy_video_ports(pci_bus_to_hose(PCI_BUS(devbusfn)))) {
printf("PCI VGA enable failed\n");
return 0;
}
/* return the pci device info, that we'll need later */
return PCI_BUS(devbusfn) << 8 |
PCI_DEV(devbusfn) << 3 | (PCI_FUNC(devbusfn)&7);
}
return 0;
}
/* Find the base address to talk tot he HDA codec.
*/
static u32 get_hda_base(void)
{
pci_dev_t devbusfn;
u32 pci_mem_base;
devbusfn = pci_find_devices(supported, 0);
if (devbusfn < 0) {
printf("Audio: Controller not found !\n");
return 0;
}
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_mem_base = pci_mem_to_phys(devbusfn, pci_mem_base);
return pci_mem_base;
}
int rtl8139_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8139 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8139\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8139#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)bus_to_phys(iobase);
dev->init = rtl8139_probe;
dev->halt = rtl_disable;
dev->send = rtl_transmit;
dev->recv = rtl_poll;
#ifdef CONFIG_MCAST_TFTP
dev->mcast = rtl_bcast_addr;
#endif
eth_register (dev);
card_number++;
pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
udelay (10 * 1000);
}
return card_number;
}
unsigned int pci_video_init (void)
{
GraphicDevice *dev = &mb862xx;
pci_dev_t devbusfn;
u16 device;
if ((devbusfn = pci_find_devices (supported, 0)) < 0) {
puts("controller not present\n");
return 0;
}
/* PCI setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &dev->frameAdrs);
dev->frameAdrs = pci_mem_to_phys (devbusfn, dev->frameAdrs);
if (dev->frameAdrs == 0) {
puts ("PCI config: failed to get base address\n");
return 0;
}
dev->pciBase = dev->frameAdrs;
puts("Coral-");
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &device);
switch (device) {
case PCI_DEVICE_ID_CORAL_P:
puts("P\n");
break;
case PCI_DEVICE_ID_CORAL_PA:
puts("PA\n");
break;
default:
puts("Unknown\n");
return 0;
}
/* Setup clocks and memory mode for Coral-P(A) */
HOST_WR_REG(GC_CCF, CONFIG_SYS_MB862xx_CCF);
udelay (200);
HOST_WR_REG(GC_MMR, CONFIG_SYS_MB862xx_MMR);
udelay (100);
return dev->frameAdrs;
}
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **ret_hccr, struct ehci_hcor **ret_hcor)
{
pci_dev_t pdev;
#ifdef CONFIG_PCI_EHCI_DEVICE
pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
#else
pdev = pci_find_class(PCI_CLASS_SERIAL_USB_EHCI, index);
#endif
if (pdev < 0) {
printf("EHCI host controller not found\n");
return -1;
}
ehci_pci_common_init(pdev, ret_hccr, ret_hcor);
return 0;
}
/*
* Initialize the AMD ethernet controllers.
*/
int am79c95x_init(void)
{
pci_dev_t devno;
int i;
/*
* Set interrupt line for Linux.
*/
for (i = 0; i < 2; i++) {
if ((devno = pci_find_devices(am79c95x_ids, i)) < 0)
break;
pci_write_config_byte(devno, PCI_INTERRUPT_LINE, 2+i);
}
if (i < 2)
printf("Error: Only %d AMD Ethernet Controller found!\n", i);
return 0;
}
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
int ehci_hcd_init(void)
{
pci_dev_t pdev;
uint32_t addr;
pdev = pci_find_devices(ehci_pci_ids, CONFIG_PCI_EHCI_DEVICE);
if (pdev == -1) {
printf("EHCI host controller not found\n");
return -1;
}
pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
hccr = (struct ehci_hccr *)addr;
hcor = (struct ehci_hcor *)((uint32_t) hccr +
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
return 0;
}
void pci_ftpci_init(void)
{
struct ftpci100_data *priv = NULL;
struct pci_controller *hose = (struct pci_controller *)&local_hose;
pci_dev_t bridge_num;
struct pci_device_id bridge_ids[] = {
{FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
{0, 0}
};
priv = malloc(sizeof(struct ftpci100_data));
if (!priv) {
printf("%s(): failed to malloc priv\n", __func__);
return;
}
memset(priv, 0, sizeof(struct ftpci100_data));
ftpci_preinit(priv);
debug("Device bus dev func deviceID vendorID pin address" \
" size class\n");
pci_bus_scan(priv);
/*
* Setup the PCI Bridge Window to 1GB,
* it will cause USB OHCI Host controller Unrecoverable Error
* if it is not set.
*/
bridge_num = pci_find_devices(bridge_ids, 0);
if (bridge_num == -1) {
printf("PCI Bridge not found\n");
return;
}
pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
FTPCI100_BASE_ADR_SIZE(1024));
}
int rtl8169_initialize(bd_t *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *) devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
eth_register (dev);
rtl_init(dev, bis);
card_number++;
}
return card_number;
}
int pcmcia_on(int ide_base_bus)
{
u16 dev_id;
u32 socket_status;
int slot = 0;
int cis_len;
u16 io_base;
u16 io_len;
/*
* Find the CardBus PCI device(s).
*/
if ((devbusfn = pci_find_devices(supported, 0)) < 0) {
printf("Ti CardBus: not found\n");
return 1;
}
pci_read_config_word(devbusfn, PCI_DEVICE_ID, &dev_id);
if (dev_id == 0xac56) {
debug("Enable PCMCIA Ti PCI1510\n");
} else {
debug("Enable PCMCIA Ti PCI1410A\n");
}
pcmcia_cis_ptr = CFG_PCMCIA_CIS_WIN;
cis_len = CFG_PCMCIA_CIS_WIN_SIZE;
io_base = CFG_PCMCIA_IO_WIN;
io_len = CFG_PCMCIA_IO_WIN_SIZE;
/*
* Setup the PCI device.
*/
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, &socket_base);
socket_base &= ~0xf;
socket_status = readl(socket_base+8);
if ((socket_status & 6) == 0) {
printf("Card Present: ");
switch (socket_status & 0x3c00) {
case 0x400:
printf("5V ");
break;
case 0x800:
printf("3.3V ");
break;
case 0xc00:
printf("3.3/5V ");
break;
default:
printf("unsupported Vcc ");
break;
}
switch (socket_status & 0x30) {
case 0x10:
printf("16bit PC-Card\n");
break;
case 0x20:
printf("32bit CardBus Card\n");
break;
default:
printf("8bit PC-Card\n");
break;
}
}
writeb(0x41, socket_base + 0x806); /* Enable I/O window 0 and memory window 0 */
writeb(0x0e, socket_base + 0x807); /* Reset I/O window options */
/* Careful: the linux yenta driver do not seem to reset the offset
* in the i/o windows, so leaving them non-zero is a problem */
writeb(io_base & 0xff, socket_base + 0x808); /* I/O window 0 base address */
writeb(io_base>>8, socket_base + 0x809);
writeb((io_base + io_len - 1) & 0xff, socket_base + 0x80a); /* I/O window 0 end address */
writeb((io_base + io_len - 1)>>8, socket_base + 0x80b);
writeb(0x00, socket_base + 0x836); /* I/O window 0 offset address 0x000 */
writeb(0x00, socket_base + 0x837);
writeb((pcmcia_cis_ptr&0x000ff000) >> 12,
socket_base + 0x810); /* Memory window 0 start address bits 19-12 */
writeb((pcmcia_cis_ptr&0x00f00000) >> 20,
socket_base + 0x811); /* Memory window 0 start address bits 23-20 */
writeb(((pcmcia_cis_ptr+cis_len-1) & 0x000ff000) >> 12,
socket_base + 0x812); /* Memory window 0 end address bits 19-12*/
writeb(((pcmcia_cis_ptr+cis_len-1) & 0x00f00000) >> 20,
socket_base + 0x813); /* Memory window 0 end address bits 23-20*/
writeb(0x00, socket_base + 0x814); /* Memory window 0 offset bits 19-12 */
writeb(0x40, socket_base + 0x815); /* Memory window 0 offset bits 23-20 and
* options (read/write, attribute access) */
writeb(0x00, socket_base + 0x816); /* ExCA card-detect and general control */
writeb(0x00, socket_base + 0x81e); /* ExCA global control (interrupt modes) */
writeb((pcmcia_cis_ptr & 0xff000000) >> 24,
socket_base + 0x840); /* Memory window address bits 31-24 */
/* turn off voltage */
if (voltage_set(slot, 0, 0)) {
return 1;
}
/* Enable external hardware */
if (hardware_enable(slot)) {
return 1;
}
if (check_ide_device(slot, ide_base_bus)) {
return 1;
}
return 0;
}
int
ns8382x_initialize(bd_t * bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase, status;
int i, idx = 0;
u32 phyAddress;
u32 tmp;
u32 chip_config;
while (1) { /* Find PCI device(s) */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
#ifdef NS8382X_DEBUG
printf("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
#endif
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled. */
pci_read_config_dword(devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_MEMORY)) {
printf("Error: Can not enable MEM access.\n");
continue;
} else if (!(status & PCI_COMMAND_MASTER)) {
printf("Error: Can not enable Bus Mastering.\n");
continue;
}
dev = (struct eth_device *) malloc(sizeof *dev);
if (!dev) {
printf("ns8382x: Can not allocate memory\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf(dev->name, "dp8382x#%d", card_number);
dev->iobase = bus_to_phys(iobase);
dev->priv = (void *) devno;
dev->init = ns8382x_init;
dev->halt = ns8382x_disable;
dev->send = ns8382x_send;
dev->recv = ns8382x_poll;
/* ns8382x has a non-standard PM control register
* in PCI config space. Some boards apparently need
* to be brought to D0 in this manner. */
pci_read_config_dword(devno, PCIPM, &tmp);
if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
u32 newtmp = tmp & ~(0x03 | 0x100);
pci_write_config_dword(devno, PCIPM, newtmp);
}
/* get MAC address */
for (i = 0; i < 3; i++) {
u32 data;
char *mac = (char *)&dev->enetaddr[i * 2];
OUTL(dev, i * 2, RxFilterAddr);
data = INL(dev, RxFilterData);
*mac++ = data;
*mac++ = data >> 8;
}
/* get PHY address, can't be zero */
for (phyAddress = 1; phyAddress < 32; phyAddress++) {
u32 rev, phy1;
phy1 = mdio_read(dev, phyAddress, PHYIDR1);
if (phy1 == 0x2000) { /*check for 83861/91 */
rev = mdio_read(dev, phyAddress, PHYIDR2);
if ((rev & ~(0x000f)) == 0x00005c50 ||
(rev & ~(0x000f)) == 0x00005c60) {
#ifdef NS8382X_DEBUG
printf("phy rev is %x\n", rev);
printf("phy address is %x\n",
phyAddress);
#endif
break;
}
}
}
/* set phy to autonegotiate && advertise everything */
mdio_write(dev, phyAddress, KTCR,
(ktcr_adv_1000H | ktcr_adv_1000F));
mdio_write(dev, phyAddress, ANAR,
(anar_adv_100F | anar_adv_100H | anar_adv_10H |
anar_adv_10F | anar_ieee_8023));
mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
mdio_write(dev, phyAddress, BMCR,
(Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
/* Reset the chip to erase any previous misconfiguration. */
OUTL(dev, (ChipReset), ChipCmd);
chip_config = INL(dev, ChipConfig);
/* reset the phy */
OUTL(dev, (chip_config | PhyRst), ChipConfig);
/* power up and initialize transceiver */
OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
mdio_sync(dev, EECtrl);
#ifdef NS8382X_DEBUG
{
u32 chpcfg =
INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
printf("%s: Transceiver 10%s %s duplex.\n", dev->name,
(chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
? "0" : "",
chpcfg & FullDuplex ? "full" : "half");
printf("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
dev->enetaddr[0], dev->enetaddr[1],
dev->enetaddr[2], dev->enetaddr[3],
dev->enetaddr[4], dev->enetaddr[5]);
}
#endif
/* Disable PME:
* The PME bit is initialized from the EEPROM contents.
* PCI cards probably have PME disabled, but motherboard
* implementations may have PME set to enable WakeOnLan.
* With PME set the chip will scan incoming packets but
* nothing will be written to memory. */
SavedClkRun = INL(dev, ClkRun);
OUTL(dev, SavedClkRun & ~0x100, ClkRun);
eth_register(dev);
card_number++;
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
udelay(10 * 1000);
}
return card_number;
}
/*-----------------------------------------------------------------------------
* video_hw_init --
*-----------------------------------------------------------------------------
*/
void *video_hw_init (void)
{
#ifdef CONFIG_VIDEO_SM501_PCI
unsigned int pci_mem_base, pci_mmio_base;
unsigned int id;
unsigned short device_id;
pci_dev_t devbusfn;
int mem;
#endif
unsigned int *vm, i;
memset (&sm501, 0, sizeof (GraphicDevice));
#ifdef CONFIG_VIDEO_SM501_PCI
printf("Video: ");
/* Look for SM501/SM502 chips */
devbusfn = pci_find_devices(sm501_pci_tbl, 0);
if (devbusfn < 0) {
printf ("PCI Controller not found.\n");
goto not_pci;
}
/* Setup */
pci_write_config_dword (devbusfn, PCI_COMMAND,
(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
pci_read_config_word (devbusfn, PCI_DEVICE_ID, &device_id);
pci_read_config_dword (devbusfn, PCI_REVISION_ID, &id);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0, &pci_mem_base);
pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_1, &pci_mmio_base);
sm501.frameAdrs = pci_mem_to_phys (devbusfn, pci_mem_base);
sm501.isaBase = pci_mem_to_phys (devbusfn, pci_mmio_base);
if (sm501.isaBase)
write_reg32 = write_le32;
mem = in_le32 ((unsigned __iomem *)(sm501.isaBase + 0x10));
mem = (mem & 0x0000e000) >> 13;
switch (mem) {
case 1:
mem = 8;
break;
case 2:
mem = 16;
break;
case 3:
mem = 32;
break;
case 4:
mem = 64;
break;
case 5:
mem = 2;
break;
case 0:
default:
mem = 4;
}
printf ("PCI SM50%d %d MB\n", ((id & 0xff) == 0xC0) ? 2 : 1, mem);
not_pci:
#endif
/*
* Initialization of the access to the graphic chipset Retreive base
* address of the chipset (see board/RPXClassic/eccx.c)
*/
if (!sm501.isaBase) {
sm501.isaBase = board_video_init ();
if (!sm501.isaBase)
return NULL;
}
if (!sm501.frameAdrs) {
sm501.frameAdrs = board_video_get_fb ();
if (!sm501.frameAdrs)
return NULL;
}
sm501.winSizeX = board_get_width ();
sm501.winSizeY = board_get_height ();
#if defined(CONFIG_VIDEO_SM501_8BPP)
sm501.gdfIndex = GDF__8BIT_INDEX;
sm501.gdfBytesPP = 1;
#elif defined(CONFIG_VIDEO_SM501_16BPP)
sm501.gdfIndex = GDF_16BIT_565RGB;
sm501.gdfBytesPP = 2;
#elif defined(CONFIG_VIDEO_SM501_32BPP)
sm501.gdfIndex = GDF_32BIT_X888RGB;
sm501.gdfBytesPP = 4;
#else
#error Unsupported SM501 BPP
#endif
sm501.memSize = sm501.winSizeX * sm501.winSizeY * sm501.gdfBytesPP;
/* Load Smi registers */
SmiSetRegs ();
/* (see board/RPXClassic/RPXClassic.c) */
board_validate_screen (sm501.isaBase);
/* Clear video memory */
i = sm501.memSize/4;
vm = (unsigned int *)sm501.frameAdrs;
while(i--)
*vm++ = 0;
return (&sm501);
}
