static void i82801ex_lpc_read_resources(device_t dev) { struct resource *res; /* Get the normal PCI resources of this device. */ pci_dev_read_resources(dev); /* Add the ACPI BAR */ res = pci_get_resource(dev, PMBASE); /* Add the GPIO BAR */ res = pci_get_resource(dev, GPIO_BASE); /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; }
static void sb600_lpc_read_resources(device_t dev) { struct resource *res; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ pci_get_resource(dev, 0xA0); /* SPI ROM base address */ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); }
void lpc_read_resources(device_t dev) { struct resource *res; printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - Start.\n"); /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ pci_get_resource(dev, SPIROM_BASE_ADDRESS); /* SPI ROM base address */ /* Add an extra subtractive resource for both memory and I/O. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->base = 0xff800000; res->size = 0x00800000; /* 8 MB for flash */ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ res->base = 0xfec00000; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; compact_resources(dev); printk(BIOS_DEBUG, "SB800 - Lpc.c - lpc_read_resources - End.\n"); }
/** * Read the base address registers for a given device. * * @param dev Pointer to the dev structure. * @param howmany How many registers to read. */ static void pci_read_bases(struct device *dev, unsigned int howmany) { unsigned long index; for (index = PCI_BASE_ADDRESS_0; (index < PCI_BASE_ADDRESS_0 + (howmany << 2));) { struct resource *resource; resource = pci_get_resource(dev, index); /** * Workaround for Denverton-NS silicon (Rev A0/A1 for CSME/IE, * Rev B0 for CSME only) * CSME&IEs KT IO bar must be 16-byte aligned */ if ((resource->flags & IORESOURCE_IO) && (resource->align != 4)) { printk(BIOS_DEBUG, "CSME&IEs KT IO bar must be 16-byte aligned!\n"); resource->align = 4; resource->gran = 4; resource->size = 16; } index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; } compact_resources(dev); }
static void bcm5785_ide_read_resources(device_t dev) { /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* BAR */ pci_get_resource(dev, 0x64); compact_resources(dev); }
static void rd890_read_resource(struct device *dev) { pci_dev_read_resources(dev); /* rpr6.2.(1). Write the Base Address Register (BAR) */ pci_write_config32(dev, 0xF8, 0x1); /* set IOAPIC's index as 1 and make sure no one changes it. */ pci_get_resource(dev, 0xFC); /* APIC located in sr5690 */ compact_resources(dev); }
static void smbus_read_resources(struct device *dev) { struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_IO_BASE; res->size = 32; res->limit = res->base + res->size - 1; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; /* Also add MMIO resource */ res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); }
static void mcp55_sm_read_resources(device_t dev) { unsigned long index; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); for (index = 0x60; index <= 0x68; index+=4) { // We got another 3. pci_get_resource(dev, index); } compact_resources(dev); }
static void bcm5785_sb_read_resources(device_t dev) { struct resource *res; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); /* Get Resource for SMBUS */ pci_get_resource(dev, 0x90); compact_resources(dev); /* Add an extra subtractive resource for both memory and I/O */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; }
static void rangeley_smbus_read_resources(struct device *dev) { struct resource *res; /* * The SMBus has two BARS. * BAR0 - MMIO, not used at boot time * BAR4 - IO, Used to talk to the SMBUS during boot, so we maintain * the default setting in the resource allocator. */ res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = SMBUS_IO_BASE; res->size = 32; res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; }
void cardbus_read_resources(device_t dev) { resource_t moving_base, moving_limit, moving; unsigned long type; u16 ctl; /* See if needs a card control registers base address. */ pci_get_resource(dev, PCI_BASE_ADDRESS_0); compact_resources(dev); /* See which bridge I/O resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_0); moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_0); moving = moving_base & moving_limit; /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, PCI_CB_IO_BASE_0, IORESOURCE_IO); cardbus_size_bridge_resource(dev, PCI_CB_IO_BASE_0); /* See which bridge I/O resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_IO_BASE_1); moving_limit = pci_moving_config32(dev, PCI_CB_IO_LIMIT_1); moving = moving_base & moving_limit; /* Initialize the I/O space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_IO_SIZE, PCI_CB_IO_BASE_1, IORESOURCE_IO); /* If I can, enable prefetch for mem0. */ ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; ctl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; ctl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; pci_write_config16(dev, PCI_CB_BRIDGE_CONTROL, ctl); ctl = pci_read_config16(dev, PCI_CB_BRIDGE_CONTROL); /* See which bridge memory resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_0); moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_0); moving = moving_base & moving_limit; /* Initialize the memory space constraints on the current bus. */ type = IORESOURCE_MEM; if (ctl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) type |= IORESOURCE_PREFETCH; cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, PCI_CB_MEMORY_BASE_0, type); if (type & IORESOURCE_PREFETCH) cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_0); /* See which bridge memory resources are implemented. */ moving_base = pci_moving_config32(dev, PCI_CB_MEMORY_BASE_1); moving_limit = pci_moving_config32(dev, PCI_CB_MEMORY_LIMIT_1); moving = moving_base & moving_limit; /* Initialize the memory space constraints on the current bus. */ cardbus_record_bridge_resource(dev, moving, CARDBUS_MEM_SIZE, PCI_CB_MEMORY_BASE_1, IORESOURCE_MEM); cardbus_size_bridge_resource(dev, PCI_CB_MEMORY_BASE_1); compact_resources(dev); }