void __pci_parse(struct pci_device *pdev)
{
/* first determine header type */
uint8_t header = pci_config_read_byte(pdev, 0x0E);
if (header == 0x00)
{
int need_eprom = 1;
/* determine bars and iobases */
for(int i = 0; i < 6; i++)
{
/* there are 6 BARs read them, check if the first byte is 1 */
uint32_t r = pci_config_read_dword(pdev, 0x10 + i * 4);
if (r & 1)
pdev->iobase = r & 0xFFFFFFFC;
else {
pdev->membase = r;
if (!r)
continue;
need_eprom = 0;
pci_config_write_dword(pdev, 0x10 + i * 4, 0xffffffff);
uint32_t size = pci_config_read_dword(pdev, 0x10 + i * 4);
size &= 0xfffffff0;
size = ~size;
size += 1;
pci_config_write_dword(pdev, 0x10 + i * 4, pdev->membase);
pdev->memsize = size;
if (pdev->memsize != 0)
printk("membase: 0x%x size: %d\n", pdev->membase, size);
}
}
if (need_eprom) {
uint32_t eprom = pci_config_read_dword(pdev, 0x30);
if (eprom) {
pci_config_write_dword(pdev, 0x30, 0xffffffff);
uint32_t size = pci_config_read_dword(pdev, 0x30);
size &= 0xfffffff0;
size = ~size;
size += 1;
pci_config_write_dword(pdev, 0x30, eprom);
printk("eprom is 0x%x && size is 0x%x\n", eprom, size);
}
}
/* read IRQ */
uint8_t irq = pci_config_read_byte(pdev, 0x3C);
pdev->irq = irq;
} else {
pci_info(pdev, "unknown header!\n");
}
}
static void pci_ptm_info(struct pci_dev *dev)
{
char clock_desc[8];
switch (dev->ptm_granularity) {
case 0:
snprintf(clock_desc, sizeof(clock_desc), "unknown");
break;
case 255:
snprintf(clock_desc, sizeof(clock_desc), ">254ns");
break;
default:
snprintf(clock_desc, sizeof(clock_desc), "%udns",
dev->ptm_granularity);
break;
}
pci_info(dev, "PTM enabled%s, %s granularity\n",
dev->ptm_root ? " (root)" : "", clock_desc);
}
static int pci_stub_probe(struct pci_dev *dev, const struct pci_device_id *id)
{
pci_info(dev, "claimed by stub\n");
return 0;
}
/**
* acpi_get_hp_hw_control_from_firmware
* @dev: the pci_dev of the bridge that has a hotplug controller
*
* Attempt to take hotplug control from firmware.
*/
int acpi_get_hp_hw_control_from_firmware(struct pci_dev *pdev)
{
const struct pci_host_bridge *host;
const struct acpi_pci_root *root;
acpi_status status;
acpi_handle chandle, handle;
struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
/*
* If there's no ACPI host bridge (i.e., ACPI support is compiled
* into the kernel but the hardware platform doesn't support ACPI),
* there's nothing to do here.
*/
host = pci_find_host_bridge(pdev->bus);
root = acpi_pci_find_root(ACPI_HANDLE(&host->dev));
if (!root)
return 0;
/*
* If _OSC exists, it determines whether we're allowed to manage
* the SHPC. We executed it while enumerating the host bridge.
*/
if (root->osc_support_set) {
if (host->native_shpc_hotplug)
return 0;
return -ENODEV;
}
/*
* In the absence of _OSC, we're always allowed to manage the SHPC.
* However, if an OSHP method is present, we must execute it so the
* firmware can transfer control to the OS, e.g., direct interrupts
* to the OS instead of to the firmware.
*
* N.B. The PCI Firmware Spec (r3.2, sec 4.8) does not endorse
* searching up the ACPI hierarchy, so the loops below are suspect.
*/
handle = ACPI_HANDLE(&pdev->dev);
if (!handle) {
/*
* This hotplug controller was not listed in the ACPI name
* space at all. Try to get ACPI handle of parent PCI bus.
*/
struct pci_bus *pbus;
for (pbus = pdev->bus; pbus; pbus = pbus->parent) {
handle = acpi_pci_get_bridge_handle(pbus);
if (handle)
break;
}
}
while (handle) {
acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
pci_info(pdev, "Requesting control of SHPC hotplug via OSHP (%s)\n",
(char *)string.pointer);
status = acpi_run_oshp(handle);
if (ACPI_SUCCESS(status))
goto got_one;
if (acpi_is_root_bridge(handle))
break;
chandle = handle;
status = acpi_get_parent(chandle, &handle);
if (ACPI_FAILURE(status))
break;
}
pci_info(pdev, "Cannot get control of SHPC hotplug\n");
kfree(string.pointer);
return -ENODEV;
got_one:
pci_info(pdev, "Gained control of SHPC hotplug (%s)\n",
(char *)string.pointer);
kfree(string.pointer);
return 0;
}