static void bootblock_southbridge_init(void)
{
pci_devfn_t dev;
/* don't walk other busses, HT is not enabled */
/* ROM decode last 8MB FF800000 - FFFFFFFF on VT8237S/VT8237A */
/* ROM decode last 4MB FFC00000 - FFFFFFFF on VT8237R */
/* Power management controller */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev != PCI_DEV_INVALID)
goto found;
/* Power management controller */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
if (dev != PCI_DEV_INVALID)
goto found;
/* Power management controller */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237A_LPC), 0);
if (dev == PCI_DEV_INVALID)
return;
found:
pci_write_config8(dev, 0x41, 0x7f);
}
static void mch_reset(void)
{
device_t dev;
unsigned long value, base;
dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0);
if (dev != PCI_DEV_INVALID) {
/* I/O space is always enables */
/* Set gpio base */
pci_write_config32(dev, 0x58, ICH5_GPIOBASE | 1);
base = ICH5_GPIOBASE;
/* Enable GPIO Bar */
value = pci_read_config32(dev, 0x5c);
value |= 0x10;
pci_write_config32(dev, 0x5c, value);
/* Set GPIO 19 mux to IO usage */
value = inl(base);
value |= (1 <<19);
outl(value, base);
/* Pull GPIO 19 low */
value = inl(base + 0x0c);
value &= ~(1 << 19);
outl(value, base + 0x0c);
}
return;
}
static void enable_mainboard_devices(void)
{
device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
}
pci_write_config8(dev, 0x50, 0x80);
pci_write_config8(dev, 0x51, 0x1f);
#if 0
// This early setup switches IDE into compatibility mode before PCI gets
// a chance to assign I/Os
// movl $CONFIG_ADDR(0, 0x89, 0x42), %eax
// // movb $0x09, %dl
// movb $0x00, %dl
// PCI_WRITE_CONFIG_BYTE
#endif
/* we do this here as in V2, we can not yet do raw operations
* to pci!
*/
dev += 0x100; /* ICKY */
pci_write_config8(dev, 0x04, 7);
pci_write_config8(dev, 0x40, 3);
pci_write_config8(dev, 0x42, 0);
pci_write_config8(dev, 0x3c, 0xe);
pci_write_config8(dev, 0x3d, 0);
}
unsigned int get_sbdn(unsigned bus)
{
device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
return (dev >> 15) & 0x1f;
}
/* what is its usage? */
static u32 get_sbdn(u32 bus)
{
device_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus);
return (dev >> 15) & 0x1f;
}
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
* @return southbridge device number
*/
unsigned int get_sbdn(unsigned bus)
{
pci_devfn_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_CK804_PRO), bus);
return (dev >> 15) & 0x1f;
}
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_MCP55_HT), bus);
return (dev >> 15) & 0x1f;
}
static unsigned get_sbdn(unsigned bus)
{
device_t dev;
/* Find the device. */
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761),
bus);
return (dev>>15) & 0x1f;
}
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
* @return southbridge device number
*/
u32 get_sbdn(u32 bus)
{
device_t dev;
printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__);
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB700_SM),
bus);
printk(BIOS_SPEW, "SB700 - Early.c - %s - End.\n", __func__);
return (dev >> 15) & 0x1f;
}
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
* @return southbridge device number
*/
u32 get_sbdn(u32 bus)
{
device_t dev;
printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__);
//dev = PCI_DEV(bus, 0x14, 0);
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_SM),
bus);
printk(BIOS_DEBUG, "SB800 - %s - %s - End.\n", __FILE__, __func__);
return (dev >> 15) & 0x1f;
}
/**
* @brief Get SouthBridge device number
* @param[in] bus target bus number
* @return southbridge device number
*/
u32 get_sbdn(u32 bus)
{
device_t dev;
printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - Start.\n");
//dev = PCI_DEV(bus, 0x14, 0);
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_ATI_SB900_SM),
bus);
printk(BIOS_INFO, "SB900 - Early.c - get_sbdn - End.\n");
return (dev >> 15) & 0x1f;
}
/* by yhlu 2005.10 */
static unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.
*/
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
bus);
return (dev>>15) & 0x1f;
}
unsigned get_sbdn(unsigned bus)
{
pci_devfn_t dev;
/* Find the device.
* There can only be one bcm5785 on a hypertransport chain/bus.
*/
dev = pci_locate_device_on_bus(
PCI_ID(0x1166, 0x0036),
bus);
return (dev>>15) & 0x1f;
}
static void main(unsigned long bist)
{
device_t dev;
/* Enable VGA; 32MB buffer. */
pci_write_config8(0, 0xe1, 0xdd);
/*
* Disable the firewire stuff, which apparently steps on IO 0+ on
* reset. Doh!
*/
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_6305), 0);
if (dev != PCI_DEV_INVALID)
pci_write_config8(dev, 0x15, 0x1c);
enable_vt8235_serial();
console_init();
enable_smbus();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
// init_timer();
post_code(0x05);
print_debug(" Enabling mainboard devices\n");
enable_mainboard_devices();
print_debug(" Enabling shadow ram\n");
enable_shadow_ram();
ddr_ram_setup((const struct mem_controller *)0);
if (bist == 0)
early_mtrr_init();
//dump_pci_devices();
}
