static void pch_pcie_pm_late(struct device *dev)
{
enum aspm_type apmc;
u32 reg32;
/* Set 0x314 = 0x743a361b */
pci_mmio_write_config32(dev, 0x314, 0x743a361b);
/* Set 0x318[31:16] = 0x1414 */
reg32 = pci_mmio_read_config32(dev, 0x318);
reg32 &= 0x0000ffff;
reg32 |= 0x14140000;
pci_mmio_write_config32(dev, 0x318, reg32);
/* Set 0x324[5] = 1 */
reg32 = pci_mmio_read_config32(dev, 0x324);
reg32 |= (1 << 5);
pci_mmio_write_config32(dev, 0x324, reg32);
/* Set 0x330[7:0] = 0x40 */
reg32 = pci_mmio_read_config32(dev, 0x330);
reg32 &= ~(0xff);
reg32 |= 0x40;
pci_mmio_write_config32(dev, 0x330, reg32);
/* Set 0x33C[24:0] = 0x854c74 */
reg32 = pci_mmio_read_config32(dev, 0x33c);
reg32 &= 0xff000000;
reg32 |= 0x00854c74;
pci_mmio_write_config32(dev, 0x33c, reg32);
/* No IO-APIC, Disable EOI forwarding */
reg32 = pci_read_config32(dev, 0xd4);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xd4, reg32);
/* Get configured ASPM state */
apmc = pci_read_config32(dev, 0x50) & 3;
/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
if (apmc == PCIE_ASPM_BOTH) {
reg32 = pci_read_config32(dev, 0xe8);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xe8, reg32);
}
}
unsigned int pciexp_find_extended_cap(device_t dev, unsigned int cap)
{
unsigned int this_cap_offset, next_cap_offset;
unsigned int this_cap, cafe;
this_cap_offset = PCIE_EXT_CAP_OFFSET;
do {
this_cap = pci_mmio_read_config32(dev, this_cap_offset);
next_cap_offset = this_cap >> 20;
this_cap &= 0xffff;
cafe = pci_mmio_read_config32(dev, this_cap_offset + 4);
cafe &= 0xffff;
if (this_cap == cap)
return this_cap_offset;
else if (cafe == cap)
return this_cap_offset + 4;
else
this_cap_offset = next_cap_offset;
} while (next_cap_offset != 0);
return 0;
}
static void i82801ix_pcie_init(const config_t *const info)
{
device_t pciePort[6];
int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */
u32 reg32;
/* PCIe - BIOS must program... */
for (i = 0; i < 6; ++i) {
pciePort[i] = dev_find_slot(0, PCI_DEVFN(0x1c, i));
if (!pciePort[i]) {
printk(BIOS_EMERG, "PCIe port 00:1c.%x", i);
die(" is not listed in devicetree.\n");
}
#if CONFIG_MMCONF_SUPPORT
reg32 = pci_mmio_read_config32(pciePort[i], 0x300);
pci_mmio_write_config32(pciePort[i], 0x300, reg32 | (1 << 21));
pci_mmio_write_config8(pciePort[i], 0x324, 0x40);
#else
#error "MMIO needed for ICH9 PCIe"
#endif
}
if (LPC_IS_MOBILE(dev_find_slot(0, PCI_DEVFN(0x1f, 0)))) {
for (i = 0; i < 6; ++i) {
if (pciePort[i]->enabled) {
reg32 = pci_read_config32(pciePort[i], 0xe8);
reg32 |= 1;
pci_write_config32(pciePort[i], 0xe8, reg32);
}
}
}
for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) {
/* Only for the top disabled ports. */
#if CONFIG_MMCONF_SUPPORT
reg32 = pci_mmio_read_config32(pciePort[i], 0x300);
reg32 |= 0x3 << 16;
pci_mmio_write_config32(pciePort[i], 0x300, reg32);
#else
#error "MMIO needed for ICH9 PCIe"
#endif
}
/* Set slot implemented, slot number and slot power limits. */
for (i = 0; i < 6; ++i) {
const device_t dev = pciePort[i];
u32 xcap = pci_read_config32(dev, D28Fx_XCAP);
if (info->pcie_slot_implemented & (1 << i))
xcap |= PCI_EXP_FLAGS_SLOT;
else
xcap &= ~PCI_EXP_FLAGS_SLOT;
pci_write_config32(dev, D28Fx_XCAP, xcap);
if (info->pcie_slot_implemented & (1 << i)) {
u32 slcap = pci_read_config32(dev, D28Fx_SLCAP);
slcap &= ~(0x1fff << 19);
slcap |= (slot_number++ << 19);
slcap &= ~(0x0003 << 16);
slcap |= (info->pcie_power_limits[i].scale << 16);
slcap &= ~(0x00ff << 7);
slcap |= (info->pcie_power_limits[i].value << 7);
pci_write_config32(dev, D28Fx_SLCAP, slcap);
}
}
/* Lock R/WO ASPM support bits. */
for (i = 0; i < 6; ++i) {
reg32 = pci_read_config32(pciePort[i], 0x4c);
pci_write_config32(pciePort[i], 0x4c, reg32);
}
}
static void pci_init(struct device *dev)
{
u16 reg16;
u32 reg32;
printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n");
/* Enable Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Set Cache Line Size to 0x10 */
// This has no effect but the OS might expect it
pci_write_config8(dev, 0x0c, 0x10);
reg16 = pci_read_config16(dev, 0x3e);
reg16 &= ~(1 << 0); /* disable parity error response */
// reg16 &= ~(1 << 1); /* disable SERR */
reg16 |= (1 << 2); /* ISA enable */
pci_write_config16(dev, 0x3e, reg16);
/* Enable IO xAPIC on this PCIe port */
reg32 = pci_read_config32(dev, 0xd8);
reg32 |= (1 << 7);
pci_write_config32(dev, 0xd8, reg32);
/* Enable Backbone Clock Gating */
reg32 = pci_read_config32(dev, 0xe1);
reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
pci_write_config32(dev, 0xe1, reg32);
#if CONFIG_MMCONF_SUPPORT
/* Set VC0 transaction class */
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_mmio_write_config32(dev, 0x114, reg32);
/* Mask completion timeouts */
reg32 = pci_mmio_read_config32(dev, 0x148);
reg32 |= (1 << 14);
pci_mmio_write_config32(dev, 0x148, reg32);
#else
#error "MMIO needed for ICH7 PCIe"
#endif
/* Enable common clock configuration */
// Are there cases when we don't want that?
reg16 = pci_read_config16(dev, 0x50);
reg16 |= (1 << 6);
pci_write_config16(dev, 0x50, reg16);
#ifdef EVEN_MORE_DEBUG
reg32 = pci_read_config32(dev, 0x20);
printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x24);
printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x28);
printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x2c);
printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32);
#endif
/* Clear errors in status registers */
reg16 = pci_read_config16(dev, 0x06);
//reg16 |= 0xf900;
pci_write_config16(dev, 0x06, reg16);
reg16 = pci_read_config16(dev, 0x1e);
//reg16 |= 0xf900;
pci_write_config16(dev, 0x1e, reg16);
}
static void azalia_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u16 reg16;
u32 reg32;
/* Find base address */
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = (u32)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
if (RCBA32(0x2030) & (1 << 31)) {
reg32 = pci_mmio_read_config32(dev, 0x120);
reg32 &= 0xf8ffff01;
reg32 |= (1 << 24); // 2 << 24 for server
reg32 |= RCBA32(0x2030) & 0xfe;
pci_mmio_write_config32(dev, 0x120, reg32);
reg16 = pci_mmio_read_config16(dev, 0x78);
reg16 |= (1 << 11);
pci_mmio_write_config16(dev, 0x78, reg16);
} else
printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 &= ~0xfe;
pci_mmio_write_config32(dev, 0x114, reg32);
// Set VCi enable bit
reg32 = pci_mmio_read_config32(dev, 0x120);
reg32 |= (1 << 31);
pci_mmio_write_config32(dev, 0x120, reg32);
// Enable HDMI codec:
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 1);
pci_write_config32(dev, 0xc4, reg32);
reg8 = pci_read_config8(dev, 0x43);
reg8 |= (1 << 6);
pci_write_config8(dev, 0x43, reg8);
/* Additional programming steps */
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 13);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 10);
pci_write_config32(dev, 0xc4, reg32);
reg32 = pci_read_config32(dev, 0xd0);
reg32 &= ~(1 << 31);
pci_write_config32(dev, 0xd0, reg32);
if (dev->device == 0x1e20) {
/* Additional step on Panther Point */
reg32 = pci_read_config32(dev, 0xc4);
reg32 |= (1 << 17);
pci_write_config32(dev, 0xc4, reg32);
}
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
/* Codec Initialization Programming Sequence */
/* Take controller out of reset */
reg32 = read32(base + 0x08);
reg32 |= (1 << 0);
write32(base + 0x08, reg32);
/* Wait 1ms */
udelay(1000);
//
reg8 = pci_read_config8(dev, 0x40); // Audio Control
reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
/* Enable dynamic clock gating */
reg8 = pci_read_config8(dev, 0x43);
reg8 &= ~0x7;
reg8 |= (1 << 2) | (1 << 0);
pci_write_config8(dev, 0x43, reg8);
}
static void azalia_init(struct device *dev)
{
u32 base;
struct resource *res;
u32 codec_mask;
u8 reg8;
u32 reg32;
#if CONFIG_MMCONF_SUPPORT
// ESD
reg32 = pci_mmio_read_config32(dev, 0x134);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_mmio_write_config32(dev, 0x134, reg32);
// Link1 description
reg32 = pci_mmio_read_config32(dev, 0x140);
reg32 &= 0xff00ffff;
reg32 |= (2 << 16);
pci_mmio_write_config32(dev, 0x140, reg32);
// Port VC0 Resource Control Register
reg32 = pci_mmio_read_config32(dev, 0x114);
reg32 &= 0xffffff00;
reg32 |= 1;
pci_mmio_write_config32(dev, 0x114, reg32);
// VCi traffic class
reg8 = pci_mmio_read_config8(dev, 0x44);
reg8 |= (7 << 0); // TC7
pci_mmio_write_config8(dev, 0x44, reg8);
// VCi Resource Control
reg32 = pci_mmio_read_config32(dev, 0x120);
reg32 |= (1 << 31);
reg32 |= (1 << 24); // VCi ID
reg32 |= (0x80 << 0); // VCi map
pci_mmio_write_config32(dev, 0x120, reg32);
#else
#error ICH7 Azalia required CONFIG_MMCONF_SUPPORT
#endif
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
pci_write_config8(dev, 0x3c, 0x0a); // unused?
// TODO Actually check if we're AC97 or HDA instead of hardcoding this
// here, in devicetree.cb and/or romstage.c.
reg8 = pci_read_config8(dev, 0x40);
reg8 |= (1 << 3); // Clear Clock Detect Bit
pci_write_config8(dev, 0x40, reg8);
reg8 &= ~(1 << 3); // Keep CLKDETCLR from clearing the bit over and over
pci_write_config8(dev, 0x40, reg8);
reg8 |= (1 << 2); // Enable clock detection
pci_write_config8(dev, 0x40, reg8);
mdelay(1);
reg8 = pci_read_config8(dev, 0x40);
printk(BIOS_DEBUG, "Azalia: codec type: %s\n", (reg8 & (1 << 1))?"Azalia":"AC97");
//
reg8 = pci_read_config8(dev, 0x40); // Audio Control
reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
pci_write_config8(dev, 0x40, reg8);
reg8 = pci_read_config8(dev, 0x4d); // Docking Status
reg8 &= ~(1 << 7); // Docking not supported
pci_write_config8(dev, 0x4d, reg8);
#if 0
/* Set routing pin */
pci_write_config32(dev, 0xf8, 0x0);
pci_write_config8(dev, 0xfc, 0xAA);
/* Set INTA */
pci_write_config8(dev, 0x63, 0x0);
/* Enable azalia, disable ac97 */
// pm_iowrite(0x59, 0xB);
#endif
res = find_resource(dev, 0x10);
if (!res)
return;
// NOTE this will break as soon as the Azalia get's a bar above
// 4G. Is there anything we can do about it?
base = (u32)res->base;
printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
codec_mask = codec_detect(base);
if (codec_mask) {
printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
codecs_init(dev, base, codec_mask);
}
}
