struct pci_bus * __devinit pcibios_scan_root(int busnum) { LIST_HEAD(resources); struct pci_bus *bus = NULL; struct pci_sysdata *sd; while ((bus = pci_find_next_bus(bus)) != NULL) { if (bus->number == busnum) { /* Already scanned */ return bus; } } /* Allocate per-root-bus (not per bus) arch-specific data. * TODO: leak; this memory is never freed. * It's arguable whether it's worth the trouble to care. */ sd = kzalloc(sizeof(*sd), GFP_KERNEL); if (!sd) { printk(KERN_ERR "PCI: OOM, not probing PCI bus %02x\n", busnum); return NULL; } sd->node = get_mp_bus_to_node(busnum); printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum); x86_pci_root_bus_resources(busnum, &resources); bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources); if (!bus) { pci_free_resource_list(&resources); kfree(sd); } return bus; }
static int __init pcibios_init(void) { struct pci_controller *pci_ctrl; struct list_head resources; struct pci_bus *bus; int next_busno = 0, i; printk("PCI: Probing PCI hardware\n"); /* Scan all of the recorded PCI controllers. */ for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { pci_ctrl->last_busno = 0xff; INIT_LIST_HEAD(&resources); pci_controller_apertures(pci_ctrl, &resources); bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, pci_ctrl->ops, pci_ctrl, &resources); pci_ctrl->bus = bus; pci_ctrl->last_busno = bus->subordinate; if (next_busno <= pci_ctrl->last_busno) next_busno = pci_ctrl->last_busno+1; } pci_bus_count = next_busno; return platform_pcibios_fixup(); }
static struct pci_bus *soc_pci_scan_bus(int nr, struct pci_sys_data *sys) { #if LINUX_VERSION_CODE < KERNEL_VERSION(3, 3, 0) return pci_scan_bus(sys->busnr, &soc_pcie_ops, sys); #else return pci_scan_root_bus(NULL, sys->busnr, &soc_pcie_ops, sys, &sys->resources); #endif }
int pci_host_common_probe(struct platform_device *pdev, struct pci_ecam_ops *ops) { const char *type; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct pci_bus *bus, *child; struct pci_config_window *cfg; struct list_head resources; type = of_get_property(np, "device_type", NULL); if (!type || strcmp(type, "pci")) { dev_err(dev, "invalid \"device_type\" %s\n", type); return -EINVAL; } of_pci_check_probe_only(); /* Parse and map our Configuration Space windows */ INIT_LIST_HEAD(&resources); cfg = gen_pci_init(dev, &resources, ops); if (IS_ERR(cfg)) return PTR_ERR(cfg); /* Do not reassign resources if probe only */ if (!pci_has_flag(PCI_PROBE_ONLY)) pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS); bus = pci_scan_root_bus(dev, cfg->busr.start, &ops->pci_ops, cfg, &resources); if (!bus) { dev_err(dev, "Scanning rootbus failed"); return -ENODEV; } pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); /* * We insert PCI resources into the iomem_resource and * ioport_resource trees in either pci_bus_claim_resources() * or pci_bus_assign_resources(). */ if (pci_has_flag(PCI_PROBE_ONLY)) { pci_bus_claim_resources(bus); } else { pci_bus_size_bridges(bus); pci_bus_assign_resources(bus); list_for_each_entry(child, &bus->children, node) pcie_bus_configure_settings(child); } pci_bus_add_devices(bus); return 0; }
static struct pci_bus __init * mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) { if (nr >= num_pcie_ports) { BUG(); return NULL; } return pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, &sys->resources); }
struct pci_bus * __init l4vpci_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *b; struct pci_dev *dev = NULL; b = pci_scan_root_bus(NULL, sys->busnr, &l4vpci_ops, sys, &sys->resources); for_each_pci_dev(dev) l4vpci_irq_enable(dev); pci_bus_add_devices(b); return b; }
static struct pci_bus __init * mv78xx0_pcie_scan_bus(int nr, struct pci_sys_data *sys) { struct pci_bus *bus; if (nr < num_pcie_ports) { bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys, &sys->resources); } else { bus = NULL; BUG(); } return bus; }
void pcibios_scan_root(int busnum) { struct pci_bus *bus; struct pci_sysdata *sd; LIST_HEAD(resources); sd = kzalloc(sizeof(*sd), GFP_KERNEL); if (!sd) { printk(KERN_ERR "PCI: OOM, skipping PCI bus %02x\n", busnum); return; } sd->node = x86_pci_root_bus_node(busnum); x86_pci_root_bus_resources(busnum, &resources); printk(KERN_DEBUG "PCI: Probing PCI hardware (bus %02x)\n", busnum); bus = pci_scan_root_bus(NULL, busnum, &pci_root_ops, sd, &resources); if (!bus) { pci_free_resource_list(&resources); kfree(sd); } }
/* * Initialization. Try all known PCI access methods. Note that we support * using both PCI BIOS and direct access: in such cases, we use I/O ports * to access config space, but we still keep BIOS order of cards to be * compatible with 2.0.X. This should go away some day. */ static int __init pcibios_init(void) { resource_size_t io_offset, mem_offset; LIST_HEAD(resources); struct pci_bus *bus; ioport_resource.start = 0xA0000000; ioport_resource.end = 0xDFFFFFFF; iomem_resource.start = 0xA0000000; iomem_resource.end = 0xDFFFFFFF; if (insert_resource(&iomem_resource, &pci_iomem_resource) < 0) panic("Unable to insert PCI IOMEM resource\n"); if (insert_resource(&ioport_resource, &pci_ioport_resource) < 0) panic("Unable to insert PCI IOPORT resource\n"); if (!pci_probe) return 0; if (pci_check_direct() < 0) { printk(KERN_WARNING "PCI: No PCI bus detected\n"); return 0; } printk(KERN_INFO "PCI: Probing PCI hardware [mempage %08x]\n", MEM_PAGING_REG); io_offset = pci_ioport_resource.start - (pci_ioport_resource.start & 0x00ffffff); mem_offset = pci_iomem_resource.start - ((pci_iomem_resource.start & 0x03ffffff) | MEM_PAGING_REG); pci_add_resource_offset(&resources, &pci_ioport_resource, io_offset); pci_add_resource_offset(&resources, &pci_iomem_resource, mem_offset); bus = pci_scan_root_bus(NULL, 0, &pci_direct_ampci, NULL, &resources); if (!bus) return 0; pcibios_resource_survey(); pci_bus_add_devices(bus); return 0; }
static struct pci_bus * __init enp2611_pci_scan_bus(int nr, struct pci_sys_data *sys) { return pci_scan_root_bus(NULL, sys->busnr, &enp2611_pci_ops, sys, &sys->resources); }
static int versatile_pci_probe(struct platform_device *pdev) { struct resource *res; int ret, i, myslot = -1; u32 val; void __iomem *local_pci_cfg_base; struct pci_bus *bus; LIST_HEAD(pci_res); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); versatile_pci_base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(versatile_pci_base)) return PTR_ERR(versatile_pci_base); res = platform_get_resource(pdev, IORESOURCE_MEM, 1); versatile_cfg_base[0] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(versatile_cfg_base[0])) return PTR_ERR(versatile_cfg_base[0]); res = platform_get_resource(pdev, IORESOURCE_MEM, 2); versatile_cfg_base[1] = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(versatile_cfg_base[1])) return PTR_ERR(versatile_cfg_base[1]); ret = versatile_pci_parse_request_of_pci_ranges(&pdev->dev, &pci_res); if (ret) return ret; /* * We need to discover the PCI core first to configure itself * before the main PCI probing is performed */ for (i = 0; i < 32; i++) { if ((readl(versatile_cfg_base[0] + (i << 11) + PCI_VENDOR_ID) == VP_PCI_DEVICE_ID) && (readl(versatile_cfg_base[0] + (i << 11) + PCI_CLASS_REVISION) == VP_PCI_CLASS_ID)) { myslot = i; break; } } if (myslot == -1) { dev_err(&pdev->dev, "Cannot find PCI core!\n"); return -EIO; } /* * Do not to map Versatile FPGA PCI device into memory space */ pci_slot_ignore |= (1 << myslot); dev_info(&pdev->dev, "PCI core found (slot %d)\n", myslot); writel(myslot, PCI_SELFID); local_pci_cfg_base = versatile_cfg_base[1] + (myslot << 11); val = readl(local_pci_cfg_base + PCI_COMMAND); val |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE; writel(val, local_pci_cfg_base + PCI_COMMAND); /* * Configure the PCI inbound memory windows to be 1:1 mapped to SDRAM */ writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_0); writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_1); writel(PHYS_OFFSET, local_pci_cfg_base + PCI_BASE_ADDRESS_2); /* * For many years the kernel and QEMU were symbiotically buggy * in that they both assumed the same broken IRQ mapping. * QEMU therefore attempts to auto-detect old broken kernels * so that they still work on newer QEMU as they did on old * QEMU. Since we now use the correct (ie matching-hardware) * IRQ mapping we write a definitely different value to a * PCI_INTERRUPT_LINE register to tell QEMU that we expect * real hardware behaviour and it need not be backwards * compatible for us. This write is harmless on real hardware. */ writel(0, versatile_cfg_base[0] + PCI_INTERRUPT_LINE); pci_add_flags(PCI_ENABLE_PROC_DOMAINS); pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC); bus = pci_scan_root_bus(&pdev->dev, 0, &pci_versatile_ops, NULL, &pci_res); if (!bus) return -ENOMEM; pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci); pci_assign_unassigned_bus_resources(bus); pci_bus_add_devices(bus); return 0; }