void pci_init_board(void) { EFI_STATUS status; tnc_hose.first_busno = 0; tnc_hose.last_busno = 0xff; pci_set_region(tnc_hose.regions + 0, 0, 0, gd->ram_size, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); pci_set_region(tnc_hose.regions + 1, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM); pci_set_region(tnc_hose.regions + 2, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO); tnc_hose.region_count = 3; pci_setup_type1(&tnc_hose); pci_register_hose(&tnc_hose); tnc_hose.last_busno = pci_hose_scan(&tnc_hose); /* call into FspNotify */ printf("Calling into FSP (notify phase EnumInitPhaseAfterPciEnumeration): "); if ((status = FspNotifyWrapper(NULL, EnumInitPhaseAfterPciEnumeration)) != FSP_SUCCESS) printf("fail, error code %x\n", status); else printf("OK\n"); }
void pci_init_board(void) { struct pci_controller *hose = &x86_hose; /* Stop using the early hose */ gd->hose = NULL; board_pci_setup_hose(hose); pci_setup_type1(hose); pci_register_hose(hose); board_pci_pre_scan(hose); hose->last_busno = pci_hose_scan(hose); board_pci_post_scan(hose); }
void pci_init_board(void) { coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; coreboot_hose.last_busno = 0; pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, PCI_REGION_MEM); coreboot_hose.region_count = 1; pci_setup_type1(&coreboot_hose); pci_register_hose(&coreboot_hose); pci_hose_scan(&coreboot_hose); }
int pci_early_init_hose(struct pci_controller **hosep) { struct pci_controller *hose; hose = calloc(1, sizeof(struct pci_controller)); if (!hose) return -ENOMEM; board_pci_setup_hose(hose); pci_setup_type1(hose); hose->last_busno = pci_hose_scan(hose); gd->hose = hose; *hosep = hose; return 0; }
void pci_sc520_init(struct pci_controller *hose) { hose->first_busno = 0; hose->last_busno = 0xff; hose->region_count = pci_set_regions(hose); pci_setup_type1(hose, SC520_REG_ADDR, SC520_REG_DATA); pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); /* enable target memory acceses on host brige */ pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); }