static int pil_mss_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = dev_get_drvdata(pil->dev); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_Q6_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_MODEM_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_NC_HALT_BASE); /* * If the shutdown function is called before the reset function, clocks * and power will not be enabled yet. Enable them here so that register * writes performed during the shutdown succeed. */ if (drv->is_booted == false) { pil_mss_power_up(pil->dev); pil_q6v5_enable_clks(pil); } pil_q6v5_shutdown(pil); pil_q6v5_disable_clks(pil); pil_mss_power_down(pil->dev); writel_relaxed(1, drv->restart_reg); drv->is_booted = false; return 0; }
static int pil_msa_pbl_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_Q6_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_MODEM_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_NC_HALT_BASE); writel_relaxed(1, drv->restart_reg); if (drv->is_booted) { pil_msa_pbl_disable_clks(drv); pil_msa_pbl_power_down(drv); drv->is_booted = false; } return 0; }
int pil_mss_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); int ret = 0; if (drv->axi_halt_base) { pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_Q6_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_MODEM_HALT_BASE); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base + MSS_NC_HALT_BASE); } if (drv->axi_halt_q6) pil_q6v5_halt_axi_port(pil, drv->axi_halt_q6); if (drv->axi_halt_mss) pil_q6v5_halt_axi_port(pil, drv->axi_halt_mss); if (drv->axi_halt_nc) pil_q6v5_halt_axi_port(pil, drv->axi_halt_nc); ret = pil_mss_restart_reg(drv, 1); if (drv->is_booted) { pil_mss_disable_clks(drv); pil_mss_power_down(drv); drv->is_booted = false; } return ret; }
static int pil_lpass_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base); if (drv->is_booted == false) pil_lpass_enable_clks(drv); pil_q6v5_shutdown(pil); pil_lpass_disable_clks(drv); writel_relaxed(1, drv->restart_reg); drv->is_booted = false; return 0; }
static int pil_lpass_shutdown(struct pil_desc *pil) { struct q6v5_data *drv = container_of(pil, struct q6v5_data, desc); pil_q6v5_halt_axi_port(pil, drv->axi_halt_base); /* * If the shutdown function is called before the reset function, clocks * will not be enabled yet. Enable them here so that register writes * performed during the shutdown succeed. */ if (drv->is_booted == false) pil_lpass_enable_clks(drv); pil_q6v5_shutdown(pil); pil_lpass_disable_clks(drv); writel_relaxed(1, drv->restart_reg); drv->is_booted = false; return 0; }