static void pipe_dev_write(void *opaque, target_phys_addr_t offset, uint32_t value) { PipeDevice *s = (PipeDevice *)opaque; switch (offset) { case PIPE_REG_COMMAND: DR("%s: command=%d (0x%x)", __FUNCTION__, value, value); pipeDevice_doCommand(s, value); break; case PIPE_REG_SIZE: DR("%s: size=%d (0x%x)", __FUNCTION__, value, value); s->size = value; break; case PIPE_REG_ADDRESS: DR("%s: address=%d (0x%x)", __FUNCTION__, value, value); s->address = value; break; case PIPE_REG_CHANNEL: DR("%s: channel=%d (0x%x)", __FUNCTION__, value, value); s->channel = value; break; case PIPE_REG_PARAMS_ADDR_HIGH: s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL << 32) ) | ((uint64_t)value << 32); break; case PIPE_REG_PARAMS_ADDR_LOW: s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL) ) | value; break; case PIPE_REG_ACCESS_PARAMS: { struct access_params aps; uint32_t cmd; if (s->params_addr == 0) break; cpu_physical_memory_read(s->params_addr, (void*)&aps, sizeof(struct access_params)); s->channel = aps.channel; s->size = aps.size; s->address = aps.address; cmd = aps.cmd; if ((cmd != PIPE_CMD_READ_BUFFER) && (cmd != PIPE_CMD_WRITE_BUFFER)) break; pipeDevice_doCommand(s, cmd); aps.result = s->status; cpu_physical_memory_write(s->params_addr, (void*)&aps, sizeof(struct access_params)); } break; default: D("%s: offset=%d (0x%x) value=%d (0x%x)\n", __FUNCTION__, offset, offset, value, value); break; } }
static void pipe_dev_write(void *opaque, hwaddr offset, uint32_t value) { PipeDevice *s = (PipeDevice *)opaque; switch (offset) { case PIPE_REG_COMMAND: DR("%s: command=%d (0x%x)", __FUNCTION__, value, value); pipeDevice_doCommand(s, value); break; case PIPE_REG_SIZE: DR("%s: size=%d (0x%x)", __FUNCTION__, value, value); s->size = value; break; case PIPE_REG_ADDRESS: DR("%s: address=%d (0x%x)", __FUNCTION__, value, value); uint64_set_low(&s->address, value); break; case PIPE_REG_ADDRESS_HIGH: DR("%s: address_high=%d (0x%x)", __FUNCTION__, value, value); uint64_set_high(&s->address, value); break; case PIPE_REG_CHANNEL: DR("%s: channel=%d (0x%x)", __FUNCTION__, value, value); uint64_set_low(&s->channel, value); break; case PIPE_REG_CHANNEL_HIGH: DR("%s: channel_high=%d (0x%x)", __FUNCTION__, value, value); uint64_set_high(&s->channel, value); break; case PIPE_REG_PARAMS_ADDR_HIGH: s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL << 32) ) | ((uint64_t)value << 32); break; case PIPE_REG_PARAMS_ADDR_LOW: s->params_addr = (s->params_addr & ~(0xFFFFFFFFULL) ) | value; break; case PIPE_REG_ACCESS_PARAMS: { int printData = matchMeInPidTid(cpu_single_env); struct access_params aps; struct access_params_64 aps64; uint32_t cmd; /* Don't touch aps.result if anything wrong */ if (s->params_addr == 0) break; if (goldfish_guest_is_64bit()) { cpu_physical_memory_read(s->params_addr, (void*)&aps64, sizeof(aps64), printData, "pipe_reg_access_params_64"); } else { cpu_physical_memory_read(s->params_addr, (void*)&aps, sizeof(aps), printData, "pipe_reg_access_params_els"); } /* sync pipe device state from batch buffer */ if (goldfish_guest_is_64bit()) { s->channel = aps64.channel; s->size = aps64.size; s->address = aps64.address; cmd = aps64.cmd; } else { s->channel = aps.channel; s->size = aps.size; s->address = aps.address; cmd = aps.cmd; } if ((cmd != PIPE_CMD_READ_BUFFER) && (cmd != PIPE_CMD_WRITE_BUFFER)) break; pipeDevice_doCommand(s, cmd); if (goldfish_guest_is_64bit()) { aps64.result = s->status; cpu_physical_memory_write(s->params_addr, (void*)&aps64, sizeof(aps64), printData, "pipe_reg_acess_1_64"); } else { aps.result = s->status; cpu_physical_memory_write(s->params_addr, (void*)&aps, sizeof(aps), printData, "pipe_reg_acess_1_else"); } } break; default: D("%s: offset=%d (0x%x) value=%d (0x%x)\n", __FUNCTION__, offset, offset, value, value); break; } }