static uint64_t pl031_read(void *opaque, hwaddr offset,
unsigned size)
{
pl031_state *s = (pl031_state *)opaque;
if (offset >= 0xfe0 && offset < 0x1000)
return pl031_id[(offset - 0xfe0) >> 2];
switch (offset) {
case RTC_DR:
return pl031_get_count(s);
case RTC_MR:
return s->mr;
case RTC_IMSC:
return s->im;
case RTC_RIS:
return s->is;
case RTC_LR:
return s->lr;
case RTC_CR:
/* RTC is permanently enabled. */
return 1;
case RTC_MIS:
return s->is & s->im;
case RTC_ICR:
qemu_log_mask(LOG_GUEST_ERROR,
"pl031: read of write-only register at offset 0x%x\n",
(int)offset);
break;
default:
qemu_log_mask(LOG_GUEST_ERROR,
"pl031_read: Bad offset 0x%x\n", (int)offset);
break;
}
return 0;
}
static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
{
pl031_state *s = (pl031_state *)opaque;
offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000)
return pl031_id[(offset - 0xfe0) >> 2];
switch (offset) {
case RTC_DR:
return pl031_get_count(s);
case RTC_MR:
return s->mr;
case RTC_IMSC:
return s->im;
case RTC_RIS:
return s->is;
case RTC_LR:
return s->lr;
case RTC_CR:
/* RTC is permanently enabled. */
return 1;
case RTC_MIS:
return s->is & s->im;
case RTC_ICR:
fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
(int)offset);
break;
default:
cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
(int)offset);
break;
}
return 0;
}
