int rpmb_write(uint32_t *req, uint32_t req_len, uint32_t *resp, uint32_t *resp_len)
{
if (platform_boot_dev_isemmc())
return rpmb_write_emmc(dev, req, req_len, resp, resp_len);
else
return rpmb_write_ufs(dev, req, req_len, resp, resp_len);
}
void *target_mmc_device()
{
if (platform_boot_dev_isemmc())
return (void *) dev;
else
return (void *) &ufs_device;
}
int rpmb_init()
{
int ret = 0;
dev = target_mmc_device();
/* 1. Initialize storage specific data */
if (platform_boot_dev_isemmc())
{
struct mmc_device *mmc_dev = (struct mmc_device *) dev;
info.size = mmc_dev->card.rpmb_size / RPMB_MIN_BLK_SZ;
info.rel_wr_count = mmc_dev->card.rel_wr_count;
info.dev_type = EMMC_RPMB;
}
else
{
struct ufs_dev *ufs_dev = (struct ufs_dev *) dev;
ufs_rpmb_init(ufs_dev);
info.size = ufs_dev->rpmb_num_blocks;
info.rel_wr_count = ufs_dev->rpmb_rw_size;
info.dev_type = UFS_RPMB;
}
/* Register & start the listener */
ret = rpmb_listener_start();
if (ret < 0)
{
dprintf(CRITICAL, "Error registering the handler\n");
goto err;
}
err:
return ret;
}
void target_uninit(void)
{
if (platform_boot_dev_isemmc())
{
mmc_put_card_to_sleep(dev);
/* Disable HC mode before jumping to kernel */
sdhci_mode_disable(&dev->host);
}
if (crypto_initialized())
{
crypto_eng_cleanup();
clock_ce_disable(CE_INSTANCE);
}
#if VERIFIED_BOOT
#if !VBOOT_MOTA
if (is_sec_app_loaded())
{
if (send_milestone_call_to_tz() < 0)
{
dprintf(CRITICAL, "Failed to unload App for rpmb\n");
ASSERT(0);
}
}
if (rpmb_uninit() < 0)
{
dprintf(CRITICAL, "RPMB uninit failed\n");
ASSERT(0);
}
#endif
#endif
rpm_smd_uninit();
}
void target_init(void)
{
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
target_keystatus();
if (target_use_signed_kernel())
target_crypto_init_params();
platform_read_boot_config();
if (platform_boot_dev_isemmc())
target_sdc_init();
else
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
/* Storage initialization is complete, read the partition table info */
if (partition_read_table())
{
dprintf(CRITICAL, "Error reading the partition table info\n");
ASSERT(0);
}
}
void target_uninit(void)
{
if(platform_boot_dev_isemmc())
{
mmc_put_card_to_sleep(dev);
sdhci_mode_disable(&dev->host);
}
}
int rpmb_write(uint32_t *req, uint32_t req_len, uint32_t rel_wr_count, uint32_t *resp, uint32_t *resp_len)
{
int ret = 0;
if (platform_boot_dev_isemmc())
ret = rpmb_write_emmc(dev, req, req_len, rel_wr_count, resp, resp_len);
#ifdef UFS_SUPPORT
else
ret = rpmb_write_ufs(dev, req, req_len, rel_wr_count, resp, resp_len);
#endif
return ret;
}
void target_serialno(unsigned char *buf)
{
uint32_t serialno;
if (target_is_emmc_boot()) {
if (platform_boot_dev_isemmc())
serialno = mmc_get_psn();
else
serialno = board_chip_serial();
snprintf((char *)buf, 13, "%x", serialno);
}
}
void target_uninit(void)
{
if (platform_boot_dev_isemmc())
{
mmc_put_card_to_sleep(dev);
/* Disable HC mode before jumping to kernel */
sdhci_mode_disable(&dev->host);
}
if (crypto_initialized())
crypto_eng_cleanup();
rpm_smd_uninit();
}
void target_init(void)
{
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
target_keystatus();
if (target_use_signed_kernel())
target_crypto_init_params();
platform_read_boot_config();
if (platform_boot_dev_isemmc())
{
target_sdc_init();
}
else
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
/* Storage initialization is complete, read the partition table info */
if (partition_read_table())
{
dprintf(CRITICAL, "Error reading the partition table info\n");
ASSERT(0);
}
rpm_smd_init();
/* QPNP WLED init for display backlight */
pm8x41_wled_config_slave_id(PMIC_WLED_SLAVE_ID);
qpnp_wled_init();
}
void platform_uninit(void)
{
qtimer_uninit();
if (!platform_boot_dev_isemmc())
qpic_nand_uninit();
}
int rpmb_init()
{
int ret = 0;
dev = target_mmc_device();
/* 1. Initialize storage specific data */
if (platform_boot_dev_isemmc())
{
struct mmc_device *mmc_dev = (struct mmc_device *) dev;
info.size = mmc_dev->card.rpmb_size / RPMB_MIN_BLK_SZ;
if (mmc_dev->card.ext_csd[MMC_EXT_CSD_REV] < 8)
{
//as per emmc spec rel_wr_count should be 1 for emmc version < 5.1
dprintf(SPEW, "EMMC Version < 5.1\n");
info.rel_wr_count = 1;
}
else
{
if (mmc_dev->card.ext_csd[MMC_EXT_CSD_EN_RPMB_REL_WR] == 0)
{
dprintf(SPEW, "EMMC Version >= 5.1 EN_RPMB_REL_WR = 0\n");
// according to emmc version 5.1 and above if EN_RPMB_REL_WR in extended
// csd is not set the maximum number of frames that can be reliably written
// to emmc would be 2
info.rel_wr_count = 2;
}
else
{
dprintf(SPEW, "EMMC Version >= 5.1 EN_RPMB_REL_WR = 1\n");
// according to emmc version 5.1 and above if EN_RPMB_REL_WR in extended
// csd is set the maximum number of frames that can be reliably written
// to emmc would be 32
info.rel_wr_count = 32;
}
}
/*
* tz changes required for supporting
* multiple frames are not present
* force the number of frames to be minimum
* i.e. one for tz 3.0 and earlier.
*/
if( qseecom_get_version() < QSEE_VERSION_40 )
info.rel_wr_count = 1;
info.dev_type = EMMC_RPMB;
}
#ifdef UFS_SUPPORT
else
{
struct ufs_dev *ufs_dev = (struct ufs_dev *) dev;
ufs_rpmb_init(ufs_dev);
info.size = ufs_dev->rpmb_num_blocks;
info.rel_wr_count = ufs_dev->rpmb_rw_size;
info.dev_type = UFS_RPMB;
}
#endif
/* Register & start the listener */
ret = rpmb_listener_start();
if (ret < 0)
{
dprintf(CRITICAL, "Error registering the handler\n");
goto err;
}
err:
return ret;
}
void target_init(void)
{
#if VERIFIED_BOOT
#if !VBOOT_MOTA
int ret = 0;
#endif
#endif
dprintf(INFO, "target_init()\n");
spmi_init(PMIC_ARB_CHANNEL_NUM, PMIC_ARB_OWNER_ID);
target_keystatus();
if (target_use_signed_kernel())
target_crypto_init_params();
platform_read_boot_config();
#ifdef MMC_SDHCI_SUPPORT
if (platform_boot_dev_isemmc())
{
target_sdc_init();
}
#endif
#ifdef UFS_SUPPORT
if(!platform_boot_dev_isemmc())
{
ufs_device.base = UFS_BASE;
ufs_init(&ufs_device);
}
#endif
/* Storage initialization is complete, read the partition table info */
mmc_read_partition_table(0);
#if VERIFIED_BOOT
#if !VBOOT_MOTA
/* Initialize Qseecom */
ret = qseecom_init();
if (ret < 0)
{
dprintf(CRITICAL, "Failed to initialize qseecom, error: %d\n", ret);
ASSERT(0);
}
/* Start Qseecom */
ret = qseecom_tz_init();
if (ret < 0)
{
dprintf(CRITICAL, "Failed to start qseecom, error: %d\n", ret);
ASSERT(0);
}
if (rpmb_init() < 0)
{
dprintf(CRITICAL, "RPMB init failed\n");
ASSERT(0);
}
/*
* Load the sec app for first time
*/
if (load_sec_app() < 0)
{
dprintf(CRITICAL, "Failed to load App for verified\n");
ASSERT(0);
}
#endif
#endif
rpm_smd_init();
/* QPNP LED init for boot process notification */
if (board_hardware_id() == HW_PLATFORM_LIQUID){
pm8x41_wled_config_slave_id(PMIC_LED_SLAVE_ID);
qpnp_led_init(QPNP_LED_BLUE, QPNP_LED_CTRL_BASE,
QPNP_BLUE_LPG_CTRL_BASE);
}
}