void genprim_platform_methods(compile_t* c, reach_type_t* t)
{
platform_freebsd(c, t);
platform_linux(c, t);
platform_osx(c, t);
platform_windows(c, t);
platform_x86(c, t);
platform_arm(c, t);
platform_lp64(c, t);
platform_llp64(c, t);
platform_ilp32(c, t);
platform_native128(c, t);
platform_debug(c, t);
}
unsigned char c64_cia_read(unsigned char chip, unsigned char addr) {
#ifdef DEBUG
platform_debug(" (CIA read from chip %d %x) \n", chip, addr);
#endif
switch (addr) {
case 0x0: // PDRa
if (! chip) {
return 0xff;
}
return 0xd0;
break;
case 0x1: // PDRb
if (! chip) {
return 0xff;
}
reveller->abort("CIA#2 PDRb is not emulated\n");
/*
{
unsigned char data = (ciaRegister[chip].PDRb | ~ciaRegister[chip].DDRb);
if ((ciaTimers[chip].CR[0] & 0x2) || (ciaTimers[chip].CR[1] & 0x2)) {
platform_debug("CIA#%d: CRA %02x, CRB %02x\n", chip, ciaTimers[chip].CR[0], ciaTimers[chip].CR[1]);
platform_debug("Unsupported CIA Operation\n");
exit(0);
}
printf("CIA RET READa (%x %x): %x\n", ciaRegister[chip].PDRb, ciaRegister[chip].DDRb, data);
return data;
break;
}
*/
case 0x4: // timerA low
return ciaTimers[chip].counters[0] & 0xff;
break;
case 0x5: // timerA high
return (ciaTimers[chip].counters[0] >> 8) & 0xff;
break;
case 0x6: // timerB low
return ciaTimers[chip].counters[1] & 0xff;
break;
case 0x7: // timerB high
return (ciaTimers[chip].counters[1] >> 8) & 0xff;
break;
case 0xc:
return ciaRegister[chip].SDR;
break;
case 0xd: // IDR
{
unsigned char ret = ciaRegister[chip].IDR;
if (ret) {
ret |= 0x80;
}
ciaRegister[chip].IDR = 0;
#ifdef DEBUG
platform_debug("\tciaRead(): read from chip %d, addr: 0xd, returning %x\n", chip, ret);
#endif
return ret;
}
case 0xe:
#ifdef DEBUG
platform_debug("\tciaRead(): read from chip %d, addr: 0xe, returning %x\n", chip, ciaTimers[chip].CR[0]);
#endif
return ciaTimers[chip].CR[0];
break;
default:
reveller->abort("Unsupported CIA Read on chip %d: (%02x)\n", chip, addr);
}
reveller->abort("Unsupported CIA Read (%02x)\n", addr);
return 0x0;
}
void c64_cia_write(unsigned char chip, unsigned char addr, unsigned char data) {
#ifdef DEBUG
platform_debug(" (CIA write to chip %d %x) %x\n", chip, addr, data);
#endif
switch (addr) {
case 0x0: // PDRa
//ciaRegister[chip].PDRa = data;
break;
case 0x1: // PDRb
//ciaRegister[chip].PDRa = data;
break;
case 0x2: // DDRa
ciaRegister[chip].DDRa = data;
break;
case 0x3: // DDRb
ciaRegister[chip].DDRb = data;
break;
case 0x4: // Timer A Low
ciaTimers[chip].latches[0] &= 0xff00;
ciaTimers[chip].latches[0] |= data;
break;
case 0x5: // Timer A High
ciaTimers[chip].latches[0] &= 0x00ff;
ciaTimers[chip].latches[0] |= (data << 8);
// reload timer if stopped
if (! (ciaTimers[chip].CR[0] & 0x1)) {
ciaTimers[chip].counters[0] = ciaTimers[chip].latches[0];
}
break;
case 0x6: // Timer B Low
ciaTimers[chip].latches[1] &= 0xff00;
ciaTimers[chip].latches[1] |= data;
break;
case 0x7: // Timer B High
ciaTimers[chip].latches[1] &= 0x00ff;
ciaTimers[chip].latches[1] |= (data << 8);
// reload timer if stopped
if (! (ciaTimers[chip].CR[1] & 0x1)) {
ciaTimers[chip].counters[1] = ciaTimers[chip].latches[1];
}
break;
case 0x8: // TOD msec.
break;
case 0x9: // TOD sec.
break;
case 0xa: // TOD min.
break;
case 0xb: // TOD HR
break;
case 0xc: // Serial shift register
ciaRegister[chip].SDR = data;
ciaRegister[chip].IDR |= (1 << 3);
break;
case 0xd: // ICR
if (data & 0x80) {
if (data & 0x1) {
ciaTimers[chip].interrupt_enabled[0] = 1;
}
if (data & 0x2) {
ciaTimers[chip].interrupt_enabled[1] = 1;
}
if (data & 0x8) {
reveller->abort("CIA#%d enabled IRQ on SD, not supported", chip);
}
ciaRegister[chip].ICR |= (data & 0x1f);
} else {
if (data & 0x1) {
ciaTimers[chip].interrupt_enabled[0] = 0;
}
if (data & 0x2) {
ciaTimers[chip].interrupt_enabled[1] = 0;
}
ciaRegister[chip].ICR &= ~data;
}
#ifdef DEBUG
platform_debug("\tCIA#%d ICR: %x\n", chip, ciaRegister[chip].ICR );
#endif
break;
case 0xe: // CRA
c64_cia_write_cr(chip, data, 'A');
break;
case 0xf: // CRB
c64_cia_write_cr(chip, data, 'B');
break;
default:
reveller->abort("Unsupported CIA Write on chip %d: (%02x)\n", chip, addr);
}
}
