예제 #1
0
void hal_hardware_init(void)
{
	hal_xscale_core_init();

    *PXA2X0_ICMR = 0;			// IRQ Mask
    *PXA2X0_ICLR = 0;			// Route interrupts to IRQ
    *PXA2X0_ICCR = 1;

	*PXA2X0_GRER0 = 0;			// Disable rising edge detect
	*PXA2X0_GRER1 = 0;
	*PXA2X0_GRER2 = 0;

	*PXA2X0_GFER0 = 0;			// Disable falling edge detect
	*PXA2X0_GFER1 = 0;
	*PXA2X0_GFER2 = 0;

	*PXA2X0_GEDR0 = 0xffffffff;	// Clear edge detect status
	*PXA2X0_GEDR1 = 0xffffffff;
	*PXA2X0_GEDR2 = 0x0001ffff;

	plf_hardware_init();		// Perform any platform specific initializations

	*PXA2X0_OSCR = 0;			// Let the "OS" counter run
	*PXA2X0_OSMR0 = 0;

	hal_if_init();				// Set up eCos/ROM interfaces

	HAL_DCACHE_ENABLE();		// Enable caches
	HAL_ICACHE_ENABLE();
}
예제 #2
0
파일: ixp425_misc.c 프로젝트: 0xCA5A/dd-wrt
void
hal_hardware_init(void)
{
    hal_xscale_core_init();

    // all interrupt sources to IRQ and disabled
    *IXP425_INTR_SEL = 0;
    *IXP425_INTR_EN = 0;

    // Enable caches
    HAL_DCACHE_ENABLE();
    HAL_ICACHE_ENABLE();

    // Let the timer run at a default rate (for delays)
    hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);

    // Set up eCos/ROM interfaces
    hal_if_init();

    // Perform any platform specific initializations
    plf_hardware_init();

#ifdef CYGPKG_IO_PCI
    cyg_hal_plf_pci_init();
#endif
}
예제 #3
0
void hal_hardware_init(void)
{
    hal_xscale_core_init();

    *PXA2X0_ICMR = 0;           // IRQ Mask
    *PXA2X0_ICLR = 0;           // Route interrupts to IRQ
    *PXA2X0_ICCR = 1;

    *PXA2X0_GRER0 = 0;          // Disable rising edge detect
    *PXA2X0_GRER1 = 0;
    *PXA2X0_GRER2 = 0;

    *PXA2X0_GFER0 = 0;          // Disable falling edge detect
    *PXA2X0_GFER1 = 0;
    *PXA2X0_GFER2 = 0;

#if defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA25X)
    *PXA2X0_GEDR0 = 0xffffffff; // Clear edge detect status
    *PXA2X0_GEDR1 = 0xffffffff;
    *PXA2X0_GEDR2 = 0x0001ffff;
#elif defined(CYGOPT_HAL_ARM_XSCALE_PXA2X0_VARIANT_PXA27X)
    *PXA2X0_ICMR2 = 0;
    *PXA2X0_ICLR2 = 0;

    *PXA2X0_GRER3 = 0;
    *PXA2X0_GFER3 = 0;

    *PXA2X0_GEDR0 = 0xfffff71b;
    *PXA2X0_GEDR1 = 0xffffffff;
    *PXA2X0_GEDR2 = 0xffffffff;
    *PXA2X0_GEDR3 = 0x1fffffff;
#endif

    plf_hardware_init();        // Perform any platform specific initializations

    *PXA2X0_OSCR = 0;           // Let the "OS" counter run
    *PXA2X0_OSMR0 = 0;

#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
    HAL_DCACHE_ENABLE();        // Enable caches
#endif
#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
    HAL_ICACHE_ENABLE();
#endif
}