static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
{
u32 ctrl = 0;
unsigned long actual_rate;
actual_rate = pll_set_rate(clk, rate, &ctrl);
if (apply) {
if (actual_rate != rate)
return -EINVAL;
if (clk->users > 0)
return -EBUSY;
pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
clk->name, rate, actual_rate);
pm_writel(PLL1, ctrl);
}
return actual_rate;
}
void mt_pll_raise_ca53_freq(u32 freq) {
pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */
}
void mt_pll_init(void)
{
int i;
/* reduce CLKSQ disable time */
write32(&mt8173_apmixed->clksq_stb_con0, (0x05 << 8) | (0x01 << 0));
/* extend PWR/ISO control timing to 1us */
write32(&mt8173_apmixed->pll_iso_con0, (0x8 << 16) | (0x8 << 0));
write32(&mt8173_apmixed->ap_pll_con6, 0x00000000);
/*************
* xPLL PWR ON
**************/
for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].pwr_reg, PLL_PWR_ON);
udelay(5); /* wait for xPLL_PWR_ON ready (min delay is 1us) */
/******************
* xPLL ISO Disable
*******************/
for (i = 0; i < APMIXED_NR_PLL; i++)
clrbits_le32(plls[i].pwr_reg, PLL_ISO);
/********************
* xPLL Frequency Set
*********************/
pll_set_rate(&plls[APMIXED_ARMCA15PLL], ARMCA15PLL_HZ);
pll_set_rate(&plls[APMIXED_ARMCA7PLL], ARMCA7PLL_HZ);
pll_set_rate(&plls[APMIXED_MAINPLL], MAINPLL_HZ);
pll_set_rate(&plls[APMIXED_UNIVPLL], UNIVPLL_HZ);
pll_set_rate(&plls[APMIXED_MMPLL], MMPLL_HZ);
pll_set_rate(&plls[APMIXED_MSDCPLL], MSDCPLL_HZ);
pll_set_rate(&plls[APMIXED_VENCPLL], VENCPLL_HZ);
pll_set_rate(&plls[APMIXED_TVDPLL], TVDPLL_HZ);
pll_set_rate(&plls[APMIXED_MPLL], MPLL_HZ);
pll_set_rate(&plls[APMIXED_VCODECPLL], VCODECPLL_HZ);
pll_set_rate(&plls[APMIXED_LVDSPLL], LVDSPLL_HZ);
pll_set_rate(&plls[APMIXED_MSDCPLL2], MSDCPLL2_HZ);
pll_set_rate(&plls[APMIXED_APLL1], APLL1_HZ);
pll_set_rate(&plls[APMIXED_APLL2], APLL2_HZ);
/***********************
* xPLL Frequency Enable
************************/
for (i = 0; i < APMIXED_NR_PLL; i++)
setbits_le32(plls[i].reg, PLL_EN);
udelay(40); /* wait for PLL stable (min delay is 20us) */
/***************
* xPLL DIV RSTB
****************/
for (i = 0; i < APMIXED_NR_PLL; i++) {
if (plls[i].rstb)
setbits_le32(plls[i].reg, plls[i].rstb);
}
/**************
* INFRA CLKMUX
***************/
/* enable infrasys DCM */
setbits_le32(&mt8173_infracfg->top_dcmctl, 0x1);
write32(&mt8173_topckgen->clk_mode, 0x1);
write32(&mt8173_topckgen->clk_mode, 0x0); /* enable TOPCKGEN */
/************
* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
*************/
/* CLK_CFG_0 */
mux_set_sel(&muxes[TOP_AXI_SEL], 5); /* 5: univpll2_d2 */
mux_set_sel(&muxes[TOP_MEM_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_DDRPHYCFG_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_MM_SEL], 1); /* 1: vencpll_d2 */
/* CLK_CFG_1 */
mux_set_sel(&muxes[TOP_PWM_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_VDEC_SEL], 1); /* 1: vcodecpll_ck */
mux_set_sel(&muxes[TOP_VENC_SEL], 1); /* 1: vcodecpll_ck */
mux_set_sel(&muxes[TOP_MFG_SEL], 1); /* 1: mmpll_ck */
/* CLK_CFG_2 */
mux_set_sel(&muxes[TOP_CAMTG_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_UART_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_SPI_SEL], 1); /* 1: syspll3_d2 */
mux_set_sel(&muxes[TOP_USB20_SEL], 1); /* 1: univpll1_d8 */
/* CLK_CFG_4 */
mux_set_sel(&muxes[TOP_MSDC30_2_SEL], 2); /* 2: msdcpll_d4 */
mux_set_sel(&muxes[TOP_MSDC30_3_SEL], 5); /* 5: msdcpll_d4 */
mux_set_sel(&muxes[TOP_AUDIO_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_AUD_INTBUS_SEL], 1); /* 1: syspll1_d4 */
/* CLK_CFG_5 */
mux_set_sel(&muxes[TOP_PMICSPI_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_SCP_SEL], 1); /* 1: syspll1_d2 */
mux_set_sel(&muxes[TOP_ATB_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_VENC_LT_SEL], 6); /* 6: univpll1_d2 */
/* CLK_CFG_6 */
mux_set_sel(&muxes[TOP_DPI0_SEL], 1); /* 1: tvdpll_d2 */
mux_set_sel(&muxes[TOP_IRDA_SEL], 1); /* 1: univpll2_d4 */
mux_set_sel(&muxes[TOP_CCI400_SEL], 5); /* 5: syspll_d2 */
mux_set_sel(&muxes[TOP_AUD_1_SEL], 1); /* 1: apll1_ck */
/* CLK_CFG_7 */
mux_set_sel(&muxes[TOP_AUD_2_SEL], 1); /* 1: apll2_ck */
mux_set_sel(&muxes[TOP_MEM_MFG_IN_SEL], 1); /* 1: mmpll_ck */
mux_set_sel(&muxes[TOP_AXI_MFG_IN_SEL], 1); /* 1: hd_faxi_ck */
mux_set_sel(&muxes[TOP_SCAM_SEL], 1); /* 1: syspll3_d2 */
/* CLK_CFG_12 */
mux_set_sel(&muxes[TOP_SPINFI_IFR_SEL], 0); /* 0: clk26m */
mux_set_sel(&muxes[TOP_HDMI_SEL], 1); /* 1: AD_HDMITX_CLK */
mux_set_sel(&muxes[TOP_DPILVDS_SEL], 1); /* 1: AD_LVDSPLL_CK */
/* CLK_CFG_13 */
mux_set_sel(&muxes[TOP_MSDC50_2_H_SEL], 2); /* 2: syspll2_d2 */
mux_set_sel(&muxes[TOP_HDCP_SEL], 2); /* 2: syspll3_d4 */
mux_set_sel(&muxes[TOP_HDCP_24M_SEL], 2); /* 2: univpll_d52 */
mux_set_sel(&muxes[TOP_RTC_SEL], 1); /* 1: clkrtc_ext */
/* CLK_CFG_3 */
mux_set_sel(&muxes[TOP_USB30_SEL], 1); /* 1: univpll3_d2 */
mux_set_sel(&muxes[TOP_MSDC50_0_H_SEL], 2); /* 2: syspll2_d2 */
mux_set_sel(&muxes[TOP_MSDC50_0_SEL], 6); /* 6: msdcpll_d4 */
mux_set_sel(&muxes[TOP_MSDC30_1_SEL], 2); /* 2: msdcpll_d4 */
/* enable scpsys clock off control */
write32(&mt8173_topckgen->clk_scp_cfg_0,
(1 << 10) | (1 << 9) | (1 << 5) | (1 << 4) | (1 << 2) |
(1 << 1) | (1 << 0));
write32(&mt8173_topckgen->clk_scp_cfg_1,
(1 << 4) | (1 << 2) | (1 << 0));
}
