static void apic_pm_suspend(void *data)
{
unsigned int l, h;
unsigned long flags;
if (apic_pm_state.perfctr_pmdev)
pm_send(apic_pm_state.perfctr_pmdev, PM_SUSPEND, data);
apic_pm_state.apic_id = apic_read(APIC_ID);
apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
apic_pm_state.apic_ldr = apic_read(APIC_LDR);
apic_pm_state.apic_dfr = apic_read(APIC_DFR);
apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
__save_flags(flags);
__cli();
disable_local_APIC();
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_ENABLE;
wrmsr(MSR_IA32_APICBASE, l, h);
__restore_flags(flags);
}
static void apic_pm_resume(void *data)
{
unsigned int l, h;
unsigned long flags;
__save_flags(flags);
__cli();
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
wrmsr(MSR_IA32_APICBASE, l, h);
apic_write(APIC_ID, apic_pm_state.apic_id);
apic_write(APIC_DFR, apic_pm_state.apic_dfr);
apic_write(APIC_LDR, apic_pm_state.apic_ldr);
apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
__restore_flags(flags);
if (apic_pm_state.perfctr_pmdev)
pm_send(apic_pm_state.perfctr_pmdev, PM_RESUME, data);
}
int pm_send_all(pm_request_t rqst, void *data)
{
struct list_head *entry;
down(&pm_devs_lock);
entry = pm_devs.next;
while (entry != &pm_devs) {
struct pm_dev *dev = list_entry(entry, struct pm_dev, entry);
if (dev->callback) {
int status = pm_send(dev, rqst, data);
if (status) {
/* return devices to previous state on
* failed suspend request
*/
if (rqst == PM_SUSPEND)
pm_undo_all(dev);
up(&pm_devs_lock);
return status;
}
}
entry = entry->next;
}
up(&pm_devs_lock);
return 0;
}
/*
* Undo incomplete request
*/
static void pm_undo_all(struct pm_dev *last)
{
struct list_head *entry = last->entry.prev;
while (entry != &pm_devs) {
struct pm_dev *dev = list_entry(entry, struct pm_dev, entry);
if (dev->state != dev->prev_state) {
/* previous state was zero (running) resume or
* previous state was non-zero (suspended) suspend
*/
pm_request_t undo = (dev->prev_state
? PM_SUSPEND:PM_RESUME);
pm_send(dev, undo, (void*) dev->prev_state);
}
entry = entry->prev;
}
}
static void power_event(struct input_handle *handle, unsigned int type,
unsigned int code, int down)
{
struct input_dev *dev = handle->dev;
printk("Entering power_event\n");
if (type != EV_KEY || type != EV_PWR) return;
if (type == EV_PWR) {
switch (code) {
case KEY_SUSPEND:
printk("Powering down entire device\n");
if (!suspend_button_pushed) {
suspend_button_pushed = 1;
schedule_work(&suspend_button_task);
}
break;
case KEY_POWER:
/* Hum power down the machine. */
break;
default:
return;
}
} else {
switch (code) {
case KEY_SUSPEND:
printk("Powering down input device\n");
/* This is risky. See pm.h for details. */
if (dev->state != PM_RESUME)
dev->state = PM_RESUME;
else
dev->state = PM_SUSPEND;
pm_send(dev->pm_dev, dev->state, dev);
break;
case KEY_POWER:
/* Turn the input device off completely ? */
break;
default:
return;
}
}
return;
}
static void apic_pm_resume(void *data)
{
unsigned int l, h;
unsigned long flags;
__save_flags(flags);
__cli();
/*
* Make sure the APICBASE points to the right address
*
* FIXME! This will be wrong if we ever support suspend on
* SMP! We'll need to do this as part of the CPU restore!
*/
rdmsr(MSR_IA32_APICBASE, l, h);
l &= ~MSR_IA32_APICBASE_BASE;
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
wrmsr(MSR_IA32_APICBASE, l, h);
apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
apic_write(APIC_ID, apic_pm_state.apic_id);
apic_write(APIC_DFR, apic_pm_state.apic_dfr);
apic_write(APIC_LDR, apic_pm_state.apic_ldr);
apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
__restore_flags(flags);
if (apic_pm_state.perfctr_pmdev)
pm_send(apic_pm_state.perfctr_pmdev, PM_RESUME, data);
}
static int do_ioctl(struct inode * inode, struct file *filp,
u_int cmd, u_long arg)
{
struct apm_user * as;
struct pm_dev * pm;
struct ipm_config conf;
as = filp->private_data;
if (check_apm_user(as, "ioctl"))
return -EIO;
memset(&conf, 0, sizeof(conf));
switch (cmd) {
case APM_IOC_SUSPEND:
pm_do_suspend(CPUMODE_SLEEP);
break;
case APM_IOC_SET_WAKEUP:
if ((pm = pm_find((pm_dev_t)arg,NULL)) == NULL)
return -EINVAL;
pm_send(pm,PM_SET_WAKEUP,NULL);
break;
case APM_IOC_SLEEP:
pm_go_sleep(arg);
break;
case APM_IOC_SET_SPROF_WIN:
sleep_to = arg * HZ;
APM_DPRINTK("do_ioctl: sleep timeout %ld\n", arg);
break;
case APM_IOC_WAKEUP_ENABLE:
PWER |= arg;
APM_DPRINTK("do_ioctl: enable wakeup source:PWER=0x%x\n", PWER);
break;
case APM_IOC_WAKEUP_DISABLE:
PWER &= ~arg;
APM_DPRINTK("do_ioctl: disable wakeup source:PWER=0x%x\n", PWER);
break;
case APM_IOC_POWEROFF:
APM_DPRINTK("do_ioctl: do power off\n");
/* here all device should response ok */
pm_send_all(PM_SUSPEND, (void *)3);
pm_do_poweroff();
pm_send_all(PM_RESUME, (void *)0);
break;
case APM_IOC_RESET_BP:
APM_DPRINTK("do_ioctl: reset bp\n");
GPCR(GPIO_BB_RESET) = GPIO_bit(GPIO_BB_RESET);
mdelay(1);
GPSR(GPIO_BB_RESET) = GPIO_bit(GPIO_BB_RESET);
break;
case APM_IOC_USEROFF_ENABLE:
APM_DPRINTK("do_ioctl: useroff support enable\n");
user_off_available = (int)arg;
break;
case APM_IOC_NOTIFY_BP:
break;
case APM_IOC_REFLASH:
cpu_proc_fin();
*(unsigned long *)(phys_to_virt(FLAG_ADDR)) = REFLASH_FLAG;
// power_ic_periph_set_usb_pull_up(0);
//LIN mdelay(1000);
//LIN let GPIO control the connectivity
#include <linux/power_ic.h>
set_GPIO_mode(GPIO_USB_READY|GPIO_OUT);
clr_GPIO(GPIO_USB_READY);
power_ic_periph_set_usb_pull_up(0);
mdelay(10);
power_ic_set_reg_bit(POWER_IC_REG_EOC_CONN_CONTROL,19,1);//LIN set USB_CNTRL(bit19) to disable emu control
mdelay(1000);
//LIN power_ic_periph_set_usb_pull_up(1);
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + CLOCK_TICK_RATE/100; /* ... in 10 ms */
MDREFR |= MDREFR_SLFRSH;
while(1);
break;
case APM_IOC_PASSTHRU:
cpu_proc_fin();
*(unsigned long *)(phys_to_virt(FLAG_ADDR)) = PASS_THRU_FLAG;
power_ic_periph_set_usb_pull_up(0);
mdelay(1000);
power_ic_periph_set_usb_pull_up(1);
/* Initialize the watchdog and let it fire */
OWER = OWER_WME;
OSSR = OSSR_M3;
OSMR3 = OSCR + CLOCK_TICK_RATE/100; /* ... in 10 ms */
MDREFR |= MDREFR_SLFRSH;
while(1);
break;
case APM_IOC_SET_IPROF_WIN:
/* set profile window size */
break;
case APM_IOC_STARTPMU:
if( pipm_start_pmu !=NULL )
pipm_start_pmu();
break;
case APM_IOC_GET_IPM_CONFIG:
get_ipm_config(&conf);
return (copy_to_user((void *)arg, &conf,sizeof(conf)))? -EFAULT:0;
break;
case APM_IOC_SET_IPM_CONFIG:
if(copy_from_user(&conf,(void *)arg,sizeof(conf)))
return -EFAULT;
return set_ipm_config(&conf);
break;
default:
return -EINVAL;
}
return 0;
}
