void spi_setup(void) { pmc_enable_peripheral_clock(ID_SPI0); pmc_enable_peripheral_clock(ID_PIOA); pio_conf_pin_to_peripheral(PIOA, 0, 25); //MISO pio_conf_pin_to_peripheral(PIOA, 0, 26); //MOSI pio_conf_pin_to_peripheral(PIOA, 0, 27); //SPCK pio_conf_pin_to_peripheral(PIOA, 0, 28); //NPCS0 pio_conf_pin_to_peripheral(PIOA, 0, 29); //NPCS1 pio_conf_pin_to_peripheral(PIOA, 0, 30); //NPSC2 pio_conf_pin_to_peripheral(PIOA, 0, 31); //NPSC3 spi_reset(SPI0); }
/*===========================================================================*/ void _pal_lld_init(const PALConfig *config) { (void)config; // Enable direct write to ODSR PIOA->PIO_OWER = 0xffffffff; PIOB->PIO_OWER = 0xffffffff; PIOC->PIO_OWER = 0xffffffff; PIOD->PIO_OWER = 0xffffffff; pmc_enable_peripheral_clock(ID_PIOA); pmc_enable_peripheral_clock(ID_PIOB); pmc_enable_peripheral_clock(ID_PIOC); pmc_enable_peripheral_clock(ID_PIOD); }
/** * @brief Low level PWM driver initialization. * * @notapi */ void pwm_lld_init(void) { #if SAM3XA_PWM_USE_CH0 pwmObjectInit(&PWMD1); #endif #if SAM3XA_PWM_USE_CH1 pwmObjectInit(&PWMD2); #endif #if SAM3XA_PWM_USE_CH2 pwmObjectInit(&PWMD3); #endif #if SAM3XA_PWM_USE_CH3 pwmObjectInit(&PWMD4); #endif #if SAM3XA_PWM_USE_CH4 pwmObjectInit(&PWMD5); #endif #if SAM3XA_PWM_USE_CH5 pwmObjectInit(&PWMD6); #endif #if SAM3XA_PWM_USE_CH6 pwmObjectInit(&PWMD7); #endif #if SAM3XA_PWM_USE_CH7 pwmObjectInit(&PWMD8); #endif // Enable clock and interrupt vector pmc_enable_peripheral_clock(ID_PWM); nvicEnableVector(PWM_IRQn, CORTEX_PRIORITY_MASK(SAM3XA_PWM_DEFAULT_IRQ_PRIORITY)); }
/* * Checking that an PWM channel is enabled. */ void test_pwm_channel_enabled() { pmc_enable_peripheral_clock(ID_PWM); pwm_reset_peripheral(); pwm_enable_channel(PWM_CHANNEL_3); TEST_ASSERT_EQUAL_HEX32(0x00000008, PWM->PWM_SR); pwm_enable_channel(PWM_CHANNEL_4); TEST_ASSERT_EQUAL_HEX32(0x00000018, PWM->PWM_SR); }
/** * @brief Configures and activates the GPT peripheral. * * @param[in] gptp pointer to the @p GPTDriver object * * @notapi */ void gpt_lld_start(GPTDriver *gptp) { uint32_t clks = TC_CMR_TCCLKS_TIMER_CLOCK5; pmc_enable_peripheral_clock(gptp->peripheral_id); uint32_t irq_priority = gptp->config->irq_priority ? gptp->config->irq_priority : SAM3XA_TC_DEFAULT_IRQ_PRIORITY; chDbgCheck(CORTEX_IS_VALID_KERNEL_PRIORITY(gptp->config->irq_priority), "GPTP irq_priority"); nvicEnableVector(gptp->irq_id, CORTEX_PRIORITY_MASK(irq_priority)); if (gptp->config->bmr & TC_BMR_QDEN) { /* Quad decode mode */ clks = TC_CMR_TCCLKS_XC0; } else { if (gptp->config->frequency == SAM3XA_GPT_TIMER_CLOCK1_FREQ) { clks = TC_CMR_TCCLKS_TIMER_CLOCK1; } else if (gptp->config->frequency == SAM3XA_GPT_TIMER_CLOCK2_FREQ) { clks = TC_CMR_TCCLKS_TIMER_CLOCK2; } else if (gptp->config->frequency == SAM3XA_GPT_TIMER_CLOCK3_FREQ) { clks = TC_CMR_TCCLKS_TIMER_CLOCK3; } else if (gptp->config->frequency == SAM3XA_GPT_TIMER_CLOCK4_FREQ) { clks = TC_CMR_TCCLKS_TIMER_CLOCK4; } else { chDbgAssert(0, "GPT invalid frequency selection", "invalid frequency"); } } if (gptp->counter != NULL) { gptp->counter->TC_BMR = gptp->config->bmr; gptp->counter->TC_QIER = gptp->config->qier; gptp->counter->TC_FMR = gptp->config->fmr; } if (gptp->config->bmr & TC_BMR_QDEN) { /* Quad decode mode */ gptp->channel->TC_CMR = clks; gptp->channel->TC_CCR = TC_CCR_CLKEN; if (gptp->counter != NULL) { // Start the counter gptp->counter->TC_BCR = TC_BCR_SYNC; } } else { /* Wave mode, Increment until RC */ gptp->channel->TC_CMR = clks | TC_CMR_WAVE | TC_CMR_WAVSEL_UP_RC; gptp->channel->TC_CCR = TC_CCR_CLKDIS; } }
/** * @brief Configures and activates the SPI peripheral. * * @param[in] spip pointer to the @p SPIDriver object * * @notapi */ void spi_lld_start(SPIDriver *spip) { uint8_t scbr = spip->config->speed == 0 ? 0xFF : SystemCoreClock < spip->config->speed ? 0x01 : SystemCoreClock / spip->config->speed > 0xFF ? 0xFF : SystemCoreClock / spip->config->speed; if (spip->state == SPI_STOP) { uint32_t irq_priority = spip->config->irq_priority ? spip->config->irq_priority : SAM3XA_SPI_DEFAULT_IRQ_PRIORITY; chDbgCheck(CORTEX_IS_VALID_KERNEL_PRIORITY(irq_priority), "SPI irq_priority"); pmc_enable_peripheral_clock(spip->peripheral_id); nvicEnableVector(spip->irq_id, CORTEX_PRIORITY_MASK(irq_priority)); spip->spi->SPI_CR = SPI_CR_SPIDIS; spip->spi->SPI_CR = SPI_CR_SWRST; spip->spi->SPI_CR = SPI_CR_SWRST; spip->spi->SPI_MR = SPI_MR_MSTR | SPI_MR_MODFDIS; spip->spi->SPI_CSR[0] = SPI_CSR_BITS_8_BIT | SPI_CSR_CSAAT | SPI_CSR_SCBR(scbr) | ( spip->config->spi_mode == 1 ? 0 : spip->config->spi_mode == 2 ? SPI_CSR_CPOL | SPI_CSR_NCPHA : spip->config->spi_mode == 3 ? SPI_CSR_CPOL : SPI_CSR_NCPHA); peripheral_pin_apply(&spip->config->spck_pin); peripheral_pin_apply(&spip->config->miso_pin); peripheral_pin_apply(&spip->config->mosi_pin); palSetPad(spip->config->cs_pin.port, spip->config->cs_pin.pin); palSetPadMode(spip->config->cs_pin.port, spip->config->cs_pin.pin, PAL_MODE_OUTPUT_OPENDRAIN); spip->spi->SPI_CR = SPI_CR_SPIEN; } else { // MMC_SD will reconfigure us without stopping spip->spi->SPI_CSR[0] = SPI_CSR_BITS_8_BIT | SPI_CSR_CSAAT | SPI_CSR_SCBR(scbr) | ( spip->config->spi_mode == 1 ? 0 : spip->config->spi_mode == 2 ? SPI_CSR_CPOL | SPI_CSR_NCPHA : spip->config->spi_mode == 3 ? SPI_CSR_CPOL : SPI_CSR_NCPHA); } }