static void it8712f_pnp_enable(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, !!dev->enabled);
pnp_exit_ext_func_mode(dev);
}
static void early_superio_config(void)
{
device_t dev;
dev=PNP_DEV(0x2e, 0x00);
pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x01, 0x94); // Extended Parport modes
pnp_write_register(dev, 0x02, 0x88); // UART power on
pnp_write_register(dev, 0x03, 0x72); // Floppy
pnp_write_register(dev, 0x04, 0x01); // EPP + SPP
pnp_write_register(dev, 0x14, 0x03); // Floppy
pnp_write_register(dev, 0x20, (0x3f0 >> 2)); // Floppy
pnp_write_register(dev, 0x23, (0x378 >> 2)); // PP base
pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
pnp_write_register(dev, 0x25, (0x2f8 >> 2)); // UART2 base
pnp_write_register(dev, 0x26, (2 << 4) | 0); // FDC + PP DMA
pnp_write_register(dev, 0x27, (6 << 4) | 7); // FDC + PP DMA
pnp_write_register(dev, 0x28, (4 << 4) | 3); // UART1,2 IRQ
/* These are the SMI status registers in the SIO: */
pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0x00); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
pnp_write_register(dev, 0x33, 0x40); // GPIO2 DIR
pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
pnp_write_register(dev, 0x35, 0xff); // GPIO3 DIR
pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
pnp_write_register(dev, 0x37, 0xe0); // GPIO4 DIR
pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
pnp_write_register(dev, 0x39, 0x80); // GPIO4 POL
pnp_exit_ext_func_mode(dev);
}
static void pilot_disable_serial(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x00);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
}
/* Serial config is a fairly standard procedure. */
static void pilot_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
static inline void w83627thg_enable_serial(device_t dev, unsigned int iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase)
{
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
void w83627hf_set_clksel_48(device_t dev)
{
unsigned port = dev >> 8;
pnp_enter_ext_func_mode(dev);
outb(0x24, port);
/* Set CLKSEL (clock input on pin 1) to 48MHz. */
outb(inb(port + 1) | (1 << 6), port + 1);
pnp_exit_ext_func_mode(dev);
}
static void sio_init(void)
{
u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV);
/* We have 24MHz input. */
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & ~0x40));
/* We have GPIO for KB/MS pin. */
reg = pnp_read_config(SERIAL_DEV, 0x2a);
pnp_write_config(SERIAL_DEV, 0x2a, (reg | 1));
/* We have all RESTOUT and even some reserved bits, too. */
reg = pnp_read_config(SERIAL_DEV, 0x2c);
pnp_write_config(SERIAL_DEV, 0x2c, (reg | 0xf0));
pnp_exit_ext_func_mode(SERIAL_DEV);
pnp_enter_ext_func_mode(ACPI_DEV);
pnp_set_logical_device(ACPI_DEV);
/*
* Set the delay rising time from PWROK_LP to PWROK_ST to
* 300 - 600ms, and 0 to vice versa.
*/
reg = pnp_read_config(ACPI_DEV, 0xe6);
pnp_write_config(ACPI_DEV, 0xe6, (reg & 0xf0));
/* 1 Use external suspend clock source 32.768KHz. Undocumented?? */
reg = pnp_read_config(ACPI_DEV, 0xe4);
pnp_write_config(ACPI_DEV, 0xe4, (reg | 0x10));
pnp_exit_ext_func_mode(ACPI_DEV);
pnp_enter_ext_func_mode(GPIO_DEV);
pnp_set_logical_device(GPIO_DEV);
/* Set memory voltage to 2.75V, vcore offset + 100mV, 1.5V chipset voltage. */
pnp_write_config(GPIO_DEV, 0x30, 0x09); /* Enable GPIO 2 & GPIO 5. */
pnp_write_config(GPIO_DEV, 0xe2, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe5, 0x00); /* No inversion */
pnp_write_config(GPIO_DEV, 0xe3, 0x03); /* 0000 0011, 0=output 1=input */
pnp_write_config(GPIO_DEV, 0xe0, 0xde); /* 1101 1110, 0=output 1=input */
pnp_write_config(GPIO_DEV, 0xe1, 0x01); /* Set output val. */
pnp_write_config(GPIO_DEV, 0xe4, 0xb4); /* Set output val (1011 0100). */
pnp_exit_ext_func_mode(GPIO_DEV);
}
static void sio_init(void)
{
u8 reg;
pnp_enter_ext_func_mode(SERIAL_DEV);
reg = pnp_read_config(SERIAL_DEV, 0x24);
/* 4 Mbit flash */
reg = (reg & ~0x30) | 0x20;
/* We have 24MHz input. */
reg &= ~0x40;
/* enable MEMW#, so flash can be written */
reg |= 0x08;
pnp_write_config(SERIAL_DEV, 0x24, reg);
}
static void superio_init(void)
{
/* Enter the configuration state. */
pnp_enter_ext_func_mode(PNP_PORT);
/* COMA */
pnp_set_logical_device(PNP_PORT, 2);
pnp_set_enable(PNP_PORT, 0);
pnp_set_iobase0(PNP_PORT, CONFIG_SERIAL_PORT);
pnp_set_irq0(PNP_PORT, 4);
pnp_set_enable(PNP_PORT, 1);
/* Exit the configuration state. */
pnp_exit_ext_func_mode(PNP_PORT);
}
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
pnp_set_logical_device(GPIO1_DEV);
pnp_write_config(GPIO1_DEV, 0x30, 0x01);
pnp_write_config(GPIO1_DEV, 0x60, 0x00);
pnp_write_config(GPIO1_DEV, 0x61, 0x00);
pnp_write_config(GPIO1_DEV, 0x62, 0x00);
pnp_write_config(GPIO1_DEV, 0x63, 0x00);
pnp_write_config(GPIO1_DEV, 0x70, 0x00);
pnp_write_config(GPIO1_DEV, 0xf0, 0xff);
pnp_write_config(GPIO1_DEV, 0xf1, 0xff);
pnp_write_config(GPIO1_DEV, 0xf2, 0x00);
pnp_exit_ext_func_mode(GPIO1_DEV);
pnp_enter_ext_func_mode(GPIO2_DEV);
pnp_set_logical_device(GPIO2_DEV);
pnp_write_config(GPIO2_DEV, 0x30, 0x01);
pnp_write_config(GPIO2_DEV, 0xf0, 0xef);
pnp_write_config(GPIO2_DEV, 0xf1, 0xff);
pnp_write_config(GPIO2_DEV, 0xf2, 0x00);
pnp_write_config(GPIO2_DEV, 0xf3, 0x00);
pnp_write_config(GPIO2_DEV, 0xf5, 0x48);
pnp_write_config(GPIO2_DEV, 0xf6, 0x00);
pnp_write_config(GPIO2_DEV, 0xf7, 0xc0);
pnp_exit_ext_func_mode(GPIO2_DEV);
pnp_enter_ext_func_mode(GPIO3_DEV);
pnp_set_logical_device(GPIO3_DEV);
pnp_write_config(GPIO3_DEV, 0x30, 0x00);
pnp_write_config(GPIO3_DEV, 0xf0, 0xff);
pnp_write_config(GPIO3_DEV, 0xf1, 0xff);
pnp_write_config(GPIO3_DEV, 0xf2, 0xff);
pnp_write_config(GPIO3_DEV, 0xf3, 0x40);
pnp_exit_ext_func_mode(GPIO3_DEV);
}
static void superio_init(void)
{
pnp_enter_ext_func_mode(0x2e);
pnp_set_logical_device(0x2e, 2); // COM-A
pnp_set_enable(0x2e, 0);
pnp_set_iobase0(0x2e, 0x3f8);
pnp_set_irq0(0x2e, 4);
pnp_set_enable(0x2e, 1);
pnp_set_logical_device(0x2e, 3); // COM-B
pnp_set_enable(0x2e, 0);
pnp_set_iobase0(0x2e, 0x2f8);
pnp_set_irq0(0x2e, 3);
pnp_set_enable(0x2e, 1);
pnp_exit_ext_func_mode(0x2e);
pnp_enter_ext_func_mode(0x4e);
// Set COM3 to sane non-conflicting values
pnp_set_logical_device(0x4e, 2); // COM-A
pnp_set_enable(0x4e, 0);
pnp_set_iobase0(0x4e, 0x3e8);
pnp_set_irq0(0x4e, 11);
pnp_set_enable(0x4e, 1);
// Set COM4 to sane non-conflicting values
pnp_set_logical_device(0x4e, 3); // COM-B
pnp_set_enable(0x4e, 0);
pnp_set_iobase0(0x4e, 0x2e8);
pnp_set_irq0(0x4e, 10);
pnp_set_enable(0x4e, 1);
pnp_exit_ext_func_mode(0x4e);
}
static void sio_init(void)
{
u8 reg;
pnp_enter_ext_func_mode(GPIO2345_DEV);
pnp_set_logical_device(GPIO2345_DEV);
/* Pin 119 ~ 120 GP21, GP20 */
reg = pnp_read_config(GPIO2345_DEV, 0x29);
pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
/* todo document this */
pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
//idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe
//val 07 XX XX XX f6 0e 00 00 00 00 ff d6 96 00 40 d0 83 00 00 07
//GPO20 - 1 = 1.82 0 = 1.92 sideport voltage
//mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V
//DDR voltage 44 45 46
/* GPO20 - sideport voltage GPO23 - mgpuV */
pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
/* GPO30 GPO33 GPO35 */
//GPO35 - loadline control 0 - enabled
//GPIO30 - unknown
//GPIO33 - unknown
pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
/* GPO40 GPO41 GPO42 GPO43 PO45 */
pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */
pnp_write_config(GPIO2345_DEV, 0xf8, 0x00); /* MFC */
pnp_write_config(GPIO2345_DEV, 0xfe, 0x07); /* trig type */
pnp_exit_ext_func_mode(GPIO2345_DEV);
}
static void early_superio_config(void)
{
pnp_devfn_t dev;
dev = PNP_DEV(0x4e, 0x00);
pnp_enter_ext_func_mode(dev);
pnp_write_register(dev, 0x02, 0x0e); // UART power
pnp_write_register(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
pnp_write_register(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
pnp_write_register(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
pnp_write_register(dev, 0x1e, 1); // no 32khz clock
pnp_write_register(dev, 0x24, (0x3f8 >> 2)); // UART1 base
pnp_write_register(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
pnp_write_register(dev, 0x2c, 0); // DMA0 FIR
pnp_write_register(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
pnp_write_register(dev, 0x31, 0xce); // GPIO1 DIR
pnp_write_register(dev, 0x32, 0x00); // GPIO1 POL
pnp_write_register(dev, 0x33, 0x0f); // GPIO2 DIR
pnp_write_register(dev, 0x34, 0x00); // GPIO2 POL
pnp_write_register(dev, 0x35, 0xa8); // GPIO3 DIR
pnp_write_register(dev, 0x36, 0x00); // GPIO3 POL
pnp_write_register(dev, 0x37, 0xa8); // GPIO4 DIR
pnp_write_register(dev, 0x38, 0x00); // GPIO4 POL
pnp_write_register(dev, 0x39, 0x00); // GPIO1 OUT
pnp_write_register(dev, 0x40, 0x80); // GPIO2/MISC OUT
pnp_write_register(dev, 0x41, 0x00); // GPIO5 OUT
pnp_write_register(dev, 0x42, 0xa8); // GPIO5 DIR
pnp_write_register(dev, 0x43, 0x00); // GPIO5 POL
pnp_write_register(dev, 0x44, 0x00); // GPIO ALT1
pnp_write_register(dev, 0x45, 0x50); // GPIO ALT2
pnp_write_register(dev, 0x46, 0x00); // GPIO ALT3
pnp_write_register(dev, 0x48, 0x55); // GPIO ALT5
pnp_write_register(dev, 0x49, 0x55); // GPIO ALT6
pnp_write_register(dev, 0x4a, 0x55); // GPIO ALT7
pnp_write_register(dev, 0x4b, 0x55); // GPIO ALT8
pnp_write_register(dev, 0x4c, 0x55); // GPIO ALT9
pnp_write_register(dev, 0x4d, 0x55); // GPIO ALT10
pnp_exit_ext_func_mode(dev);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
#if 0
uint8_t tmp = 0;
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
/* Is serial flash enabled? Then enable writing to serial flash. */
if (tmp & 0x0e) {
pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
pnp_set_logical_device(GPIO_DEV);
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
#endif
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
}
#endif
init_timer(); // Need to use TMICT to synconize FID/VID
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
/*
* The logical devices will only be involved in the ISA PnP sequence if their
* respective enable bits in IT8661F_REG_LDE are set.
*
* TODO: Find out if we actually need this (we use MB PnP mode).
*
* Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved.
*/
static void it8661f_enable_logical_devices(pnp_devfn_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, IT8661F_REG_LDE, 0x1f);
pnp_exit_ext_func_mode(dev);
}
static void it8661f_set_clkin(pnp_devfn_t dev, u8 clkin)
{
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1));
pnp_exit_ext_func_mode(dev);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
/* FIXME: This should be part of the Super I/O code/config. */
pnp_enter_ext_func_mode(SERIAL_DEV);
/* Switch CLKSEL to 24MHz (default is 48MHz). Needed for serial! */
pnp_write_config(SERIAL_DEV, 0x24, 0);
w83627ehg_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map();
console_init();
report_bist_failure(bist); /* Halt upon BIST failure. */
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
#endif
setup_coherent_ht_domain(); /* Routing table and start other core0. */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched
* becase optimize_link_coherent_ht is moved out from
* setup_coherent_ht_domain, so here need to make sure last core0 is
* started, esp for two way system (there may be APIC ID conflicts in
* that case).
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* Set up chains and store link pair for optimization later. */
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
#if CONFIG_SET_FIDVID
{
msr_t msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
#endif
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
/* It's the time to set ctrl in sysinfo now. */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* All AP stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
/* bsp switch stack to RAM and copy sysinfo RAM now. */
post_cache_as_ram();
}
/* This box has one superio
* Also set up the GPIOs from the beginning. This is the "no schematic
* but safe anyways" method.
*/
static void early_superio_config_w83627ehg(void)
{
device_t dev;
dev = DUMMY_DEV;
pnp_enter_ext_func_mode(dev);
pnp_write_config(dev, 0x24, 0xc4); // PNPCSV
pnp_write_config(dev, 0x29, 0x01); // GPIO settings
pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02
pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings?
pnp_write_config(dev, 0x2c, 0x03); // GPIO settings?
pnp_write_config(dev, 0x2d, 0x20); // GPIO settings?
dev=PNP_DEV(0x4e, W83627EHG_SP1);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 4);
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_SP2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8);
pnp_set_irq(dev, PNP_IDX_IRQ0, 3);
// pnp_write_config(dev, 0xf1, 4); // IRMODE0
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
//pnp_write_config(dev, 0xf0, 0x82);
pnp_set_enable(dev, 1);
dev=PNP_DEV(0x4e, W83627EHG_GPIO2);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 1); // Just enable it
dev=PNP_DEV(0x4e, W83627EHG_GPIO3);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output
pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0
pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient
dev=PNP_DEV(0x4e, W83627EHG_FDC);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
dev=PNP_DEV(0x4e, W83627EHG_PP);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
/* Enable HWM */
dev=PNP_DEV(0x4e, W83627EHG_HWM);
pnp_set_logical_device(dev);
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
/* The SPD is being read from the CPU1 (marked CPU2 on the board) and we
don't know how to switch the SMBus to decode the CPU0 SPDs. So, The
memory on each CPU must be an exact match.
*/
static const uint16_t spd_addr[] = {
// Node 0
RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2,
RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6,
RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3,
RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7,
// Node 1
RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2,
RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6,
RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3,
RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
/* Setup the mcp55 */
mcp55_enable_rom();
}
if (bist == 0) {
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
}
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
uart_init();
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_mb_resource_map();
print_debug("bsp_apicid=");
print_debug_hex8(bsp_apicid);
print_debug("\n");
#if CONFIG_MEM_TRAIN_SEQ == 1
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#endif
/* dump_smbus_registers(); */
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if SET_FIDVID == 1
{
msr_t msr;
msr = rdmsr(0xc0010042);
print_debug("begin msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
}
#endif
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus(); /* enable in sio_setup */
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = &sysinfo_car;
u32 bsp_apicid = 0, val, wants_reset;
u8 reg;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
sio_setup();
}
post_code(0x30);
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
post_code(0x32);
pnp_enter_ext_func_mode(SERIAL_DEV);
/* We have 24MHz input. */
reg = pnp_read_config(SERIAL_DEV, 0x24);
pnp_write_config(SERIAL_DEV, 0x24, (reg & 0xbf));
pnp_exit_ext_func_mode(SERIAL_DEV);
w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
/* Setup sysinfo defaults */
set_sysinfo_in_ram(0);
#if CONFIG_UPDATE_CPU_MICROCODE
update_microcode(val);
#endif
post_code(0x33);
cpuSetAMDMSR();
post_code(0x34);
amd_ht_init(sysinfo);
post_code(0x35);
/* Setup nodes PCI space and start core 0 AP init. */
finalize_node_setup(sysinfo);
printk(BIOS_DEBUG, "finalize_node_setup done\n");
/* Setup any mainboard PCI settings etc. */
printk(BIOS_DEBUG, "setup_mb_resource_map begin\n");
setup_mb_resource_map();
printk(BIOS_DEBUG, "setup_mb_resource_map end\n");
post_code(0x36);
/* wait for all the APs core0 started by finalize_node_setup. */
/* FIXME: A bunch of cores are going to start output to serial at once.
* It would be nice to fixup prink spinlocks for ROM XIP mode.
* I think it could be done by putting the spinlock flag in the cache
* of the BSP located right after sysinfo.
*/
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
printk(BIOS_DEBUG, "wait_all_other_cores_started()\n");
wait_all_other_cores_started(bsp_apicid);
#endif
post_code(0x38);
#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
/* FIXME: The sb fid change may survive the warm reset and only
* need to be done once.*/
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x39);
if (!warm_reset_detect(0)) { // BSP is node 0
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
}
post_code(0x3A);
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
#endif
init_timer(); /* Need to use TMICT to synconize FID/VID. */
wants_reset = mcp55_early_setup_x();
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
print_info("...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
if (wants_reset)
printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n");
post_code(0x3B);
/* It's the time to set ctrl in sysinfo now; */
printk(BIOS_DEBUG, "fill_mem_ctrl()\n");
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
post_code(0x3D);
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
post_code(0x40);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
post_code(0x41);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
// Node 0
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
// Node 1
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = &sysinfo_car;
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
}
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0);
pnp_exit_ext_func_mode(SERIAL_DEV);
setup_mb_resource_map();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
*/
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
{
msr_t msr;
msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
{
msr_t msr;
msr = rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
init_timer(); /* Need to use TMICT to synchronize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
//It's the time to set ctrl in sysinfo now;
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
/* all ap stopped? */
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
}
static void sio_init(void)
{
u8 reg;
pnp_enter_ext_func_mode(GPIO2345_DEV);
pnp_set_logical_device(GPIO2345_DEV);
/* Pin 119 ~ 120 is GP21, GP20 */
reg = pnp_read_config(GPIO2345_DEV, 0x29);
pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2));
/* Turn on the Power LED ("Suspend LED" in Super I/O) */
reg = pnp_read_config(GPIO2345_DEV, 0xf3);
pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40));
/* todo document this */
pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
/* GPO20 - sideport voltage 1 = 1.82 0 = 1.92
GPI21 - unknown input (NC?)
GPI22 - unknown input (NC?)
GPO23 - mgpuV bit0
GP24-27 - PS/2 mouse/keyb (only keyb is connected use flip interface for mouse)
*/
pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */
pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/
pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */
pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */
/* GPIO30 - unknown output, set to 0
GPI31 - unknown input NC?
GPI32 - unknown input NC?
GPIO33 - unknown output, set to 0.
GPI34 - unknown input NC?
GPO35 - loadline control 1 = enabled (2 phase clock) 0 = disabled 4 phase clock
GPIO36 - input = HT voltage 1.30V output (low) = HT voltage 1.35V
GP37 - unknown input NC? */
pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/
pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */
pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */
/* GPO40 - mgpuV bit2
GPO41 - mgpuV bit1
GPO42 - IRTX
GPO43 - IRRX
GPIO44 - memory voltage bit2 (input/outputlow)
GPIO45 - memory voltage bit1 (2.60 (000) - 2.95 (111))
GPIO46 - memory voltage bit0
GPIO47 - unknown input? */
pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */
pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */
pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */
pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */
pnp_write_config(GPIO2345_DEV, 0xf8, 0x00); /* MFC */
pnp_write_config(GPIO2345_DEV, 0xfe, 0x07); /* trig type */
pnp_exit_ext_func_mode(GPIO2345_DEV);
}
static void it8712f_pnp_enable_resources(device_t dev)
{
pnp_enter_ext_func_mode(dev);
pnp_enable_resources(dev);
pnp_exit_ext_func_mode(dev);
}
/*
* Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to
* be another serial (?), it is also deactivated on the HP machine.
*/
static void pilot_early_init(device_t dev)
{
unsigned port = dev >> 8;
print_debug("Using port: ");
print_debug_hex16(port);
print_debug("\n");
pilot_disable_serial(PNP_DEV(port, 0x1));
print_debug("disable serial 1\n");
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x3));
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, 0x60, 0x0b00);
pnp_set_iobase(dev, 0x62, 0x0b80);
pnp_set_iobase(dev, 0x64, 0x0b84);
pnp_set_iobase(dev, 0x66, 0x0b86);
pnp_set_enable(dev, 1);
pnp_exit_ext_func_mode(dev);
/*
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x3));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x3), 0);
pnp_exit_ext_func_mode(dev);
*/
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x4));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable( PNP_DEV(port, 0x4), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x5));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x5), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x6));
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x60);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x64);
pnp_set_irq(dev, PNP_IDX_IRQ0, 1);
pnp_set_drq(dev, 0x71, 3);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0xe));
pnp_set_enable(dev, 0);
pnp_set_iobase(dev, PNP_IDX_IO0, 0x70);
pnp_set_iobase(dev, PNP_IDX_IO1, 0x72);
pnp_set_irq(dev, PNP_IDX_IRQ0, 8);
pnp_set_drq(dev, 0x71, 3);
pnp_set_enable(dev, 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x7));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x7), 0);
pnp_exit_ext_func_mode(dev);
/*
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x8));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x8), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x9));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x9), 0);
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x10));
pnp_exit_ext_func_mode(dev);
pnp_enter_ext_func_mode(dev);
pnp_set_enable(PNP_DEV(port, 0x10), 0);
pnp_exit_ext_func_mode(dev);
*/
}
