void f71869ad_multifunc_init(struct device *dev)
{
const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
pnp_enter_conf_mode(dev);
/* multi-func select reg1 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
conf->multi_function_register_1);
/* multi-func select reg2 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
conf->multi_function_register_2);
/* multi-func select reg3 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
conf->multi_function_register_3);
/* multi-func select reg4 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
conf->multi_function_register_4);
/* multi-func select reg5 (CLK_TUNE_EN=0) */
pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
conf->multi_function_register_5);
pnp_exit_conf_mode(dev);
}
static void nct5104d_init(struct device *dev)
{
struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
if (!dev->enabled)
return;
pnp_enter_conf_mode(dev);
switch(dev->path.pnp.device) {
case NCT5104D_SP1:
case NCT5104D_SP2:
set_irq_trigger_type(dev, conf->irq_trigger_type != 0);
break;
case NCT5104D_SP3:
case NCT5104D_SP4:
route_pins_to_uart(dev, true);
set_irq_trigger_type(dev, conf->irq_trigger_type != 0);
break;
case NCT5104D_GPIO0:
case NCT5104D_GPIO1:
route_pins_to_uart(dev, false);
break;
default:
break;
}
pnp_exit_conf_mode(dev);
}
void f71808a_multifunc_init(struct device *dev)
{
const struct superio_fintek_f71808a_config *conf = dev->chip_info;
pnp_enter_conf_mode(dev);
/* multi-func select reg0 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG0,
conf->multi_function_register_0);
/* multi-func select reg1 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
conf->multi_function_register_1);
/* multi-func select reg2 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
conf->multi_function_register_2);
/* multi-func select reg3 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
conf->multi_function_register_3);
/* multi-func select reg4 */
pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
conf->multi_function_register_4);
pnp_exit_conf_mode(dev);
}
static void w83627dhg_enable_UR2(struct device *dev)
{
u8 reg8;
pnp_enter_conf_mode(dev);
reg8 = pnp_read_config(dev, 0x2c);
reg8 |= (0x3);
pnp_write_config(dev, 0x2c, reg8); // Set pins 78-85-> UART B
pnp_exit_conf_mode(dev);
}
/*
* Set the UART clock source.
*
* Possible UART clock source speeds are:
*
* 0 = 1.8462 MHz (default)
* 1 = 2 MHz
* 2 = 24 MHz
* 3 = 14.769 MHz
*
* The faster clocks allow for BAUD rates up to 2mbits.
*
* Warning: The kernel will need to be adjusted since it assumes
* a 1.8462 MHz clock.
*/
static void set_uart_clock_source(struct device *dev, u8 uart_clock)
{
u8 value;
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xf0);
value &= ~0x03;
value |= (uart_clock & 0x03);
pnp_write_config(dev, 0xf0, value);
pnp_exit_conf_mode(dev);
}
static void w83627ehg_pnp_enable_resources(struct device *dev)
{
pnp_enable_resources(dev);
pnp_enter_conf_mode(dev);
switch (dev->path.pnp.device) {
case W83627EHG_HWM:
printk(BIOS_DEBUG, "W83627EHG HWM SMBus enabled\n");
enable_hwm_smbus(dev);
break;
}
pnp_exit_conf_mode(dev);
}
static void init_acpi(struct device *dev)
{
u8 value;
int power_on = 1;
get_option(&power_on, "power_on_after_fail");
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xe4);
value &= ~(3 << 5);
if (power_on)
value |= (1 << 5);
pnp_write_config(dev, 0xe4, value);
pnp_exit_conf_mode(dev);
}
static void lpc47b397_pnp_enable_resources(struct device *dev)
{
pnp_enable_resources(dev);
pnp_enter_conf_mode(dev);
switch (dev->path.pnp.device) {
case LPC47B397_HWM:
printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n");
pnp_set_logical_device(dev);
enable_hwm_smbus(dev);
break;
}
/* dump_pnp_device(dev); */
pnp_exit_conf_mode(dev);
}
static void init_acpi(device_t dev)
{
u8 value = 0x20; /* TODO: 0x20 value here never used? */
int power_on = 1;
get_option(&power_on, "power_on_after_fail");
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
value = pnp_read_config(dev, 0xe4);
value &= ~(3 << 5);
if (power_on)
value |= (1 << 5);
pnp_write_config(dev, 0xe4, value);
pnp_exit_conf_mode(dev);
}
/* note: multifunc registers need to be tweaked before here */
void f71869ad_hwm_init(struct device *dev)
{
const struct superio_fintek_f71869ad_config *conf = dev->chip_info;
struct resource *res = find_resource(dev, PNP_IDX_IO0);
if (!res) {
printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
return;
}
u16 port = res->base; /* data-sheet default base = 0x229 */
printk(BIOS_INFO,
"Fintek F71869AD Super I/O HWM: Initializing Hardware Monitor..\n");
printk(BIOS_DEBUG,
"Fintek F71869AD Super I/O HWM: Base Address at 0x%x\n", port);
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
/* Fintek F71869AD HWM (ordered) programming sequence. */
/* SMBus Address p.53 */
pnp_write_index(port, HWM_SMBUS_ADDR, conf->hwm_smbus_address);
/* Configure pins 57/58 as PECI_REQ#/PECI (AMD_TSI) p.54 */
pnp_write_index(port, HWM_SMBUS_CONTROL_REG, conf->hwm_smbus_control_reg);
/* Tfan1 = Tnow + (Ta - Tb)*Ct where, */
/* FAN1_TEMP_SEL_DIG, FAN1_TEMP_SEL (Tnow) set to come from CR7Ah p.73 */
pnp_write_index(port, HWM_FAN1_TEMP_MAP_SEL, conf->hwm_fan1_temp_map_sel);
/* set FAN_PROG_SEL = 1 */
pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x8a);
/* FAN1_BASE_TEMP (Tb) set when FAN_PROG_SEL = 1, p.64-65 */
pnp_write_index(port, HWM_FAN_TYPE_SEL_REG, conf->hwm_fan_type_sel_reg);
/* set TFAN1_ADJ_SEL (Ta) p.67 to use CR7Ah p.61 */
pnp_write_index(port, HWM_FAN_MODE_SEL_REG, conf->hwm_fan_mode_sel_reg);
/* TFAN1_ADJ_{UP,DOWN}_RATE (Ct = 1/4 up & down) in 0x95 when FAN_PROG_SEL =
1, p.88 */
pnp_write_index(port, HWM_FAN1_TEMP_ADJ_RATE_REG, conf->hwm_fan1_temp_adj_rate_reg);
/* set FAN_PROG_SEL = 0 */
pnp_write_index(port, HWM_FAN_FAULT_TIME_REG, 0x0a);
/* FAN1 RPM mode p.70 */
pnp_write_index(port, HWM_FAN1_IDX_RPM_MODE, conf->hwm_fan1_idx_rpm_mode);
/* FAN1 Segment X Speed Count */
pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count);
pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count);
pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count);
pnp_exit_conf_mode(dev);
}
static void vt1211_pnp_set_resources(struct device *dev)
{
struct resource *res;
#if IS_ENABLED(CONFIG_CONSOLE_SERIAL) && IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
/* TODO: Do the same for SP2? */
if (dev->path.pnp.device == VT1211_SP1) {
for (res = dev->resource_list; res; res = res->next) {
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
return;
}
#endif
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
/* Paranoia says I should disable the device here... */
for (res = dev->resource_list; res; res = res->next) {
if (!(res->flags & IORESOURCE_ASSIGNED)) {
printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx "
"not assigned\n", dev_path(dev), res->index,
resource_type(res), res->size);
continue;
}
/* Now store the resource. */
if (res->flags & IORESOURCE_IO) {
vt1211_set_iobase(dev, res->index, res->base);
} else if (res->flags & IORESOURCE_DRQ) {
pnp_set_drq(dev, res->index, res->base);
} else if (res->flags & IORESOURCE_IRQ) {
pnp_set_irq(dev, res->index, res->base);
} else {
printk(BIOS_ERR, "ERROR: %s %02lx unknown resource "
"type\n", dev_path(dev), res->index);
return;
}
res->flags |= IORESOURCE_STORED;
report_resource_stored(dev, res, "");
}
pnp_exit_conf_mode(dev);
}
void it8728f_hwm_ec_init(struct device *dev)
{
struct superio_ite_it8728f_config *conf = dev->chip_info;
struct resource *res = find_resource(dev, PNP_IDX_IO0);
if (!res) {
printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n");
return;
}
/* I/O port for HWM is at base + 5 */
u16 port = res->base + 5;
printk(BIOS_INFO,
"ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n");
printk(BIOS_DEBUG,
"ITE IT8728F Super I/O HWM: Base Address at 0x%x\n", port);
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
/* ITE IT8728F HWM (ordered) programming sequence. */
/* configure fan polarity */
pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register);
/* enable fans 1-3 */
pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register);
/* enable termistor temps for temp1-temp3 */
pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg);
/* configure which fanX uses which tempY */
pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm);
pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm);
pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm);
pnp_exit_conf_mode(dev);
}
static void nct5104d_init(device_t dev)
{
struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
u8 reg10, reg11, reg26;
if (!dev->enabled)
return;
pnp_enter_conf_mode(dev);
//Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 |= CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
switch(dev->path.pnp.device) {
//SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5
case NCT5104D_SP1:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (conf->irq_trigger_type)
reg10 |= (1 << 5);
else
reg10 &= ~(1 << 5);
pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
break;
//SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4
case NCT5104D_SP2:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (conf->irq_trigger_type)
reg10 |= (1 << 4);
else
reg10 &= ~(1 << 4);
pnp_write_config(dev, IRQ_TYPE_SEL_CR10, reg10);
break;
//SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5
case NCT5104D_SP3:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (conf->irq_trigger_type)
reg11 |= (1 << 5);
else
reg11 &= ~(1 << 5);
pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
break;
//SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4
case NCT5104D_SP4:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (conf->irq_trigger_type)
reg11 |= (1 << 4);
else
reg11 &= ~(1 << 4);
pnp_write_config(dev, IRQ_TYPE_SEL_CR11, reg11);
break;
default:
break;
}
//Clear access control register
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 &= ~CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
pnp_exit_conf_mode(dev);
}