static void mpc55xx_interrupt_dispatch(void) { /* Acknowlege interrupt request */ rtems_vector_number vector = INTC.IACKR.B.INTVEC; /* Save machine state and enable external exceptions */ uint32_t msr = ppc_external_exceptions_enable(); /* Dispatch interrupt handlers */ bsp_interrupt_handler_dispatch( vector); /* Restore machine state */ ppc_external_exceptions_disable( msr); /* End of interrupt */ INTC.EOIR.R = 1; }
static void qoriq_interrupt_dispatch(void) { rtems_vector_number vector = qoriq.pic.iack; if (vector != SPURIOUS) { uint32_t msr = ppc_external_exceptions_enable(); bsp_interrupt_handler_dispatch(vector); ppc_external_exceptions_disable(msr); qoriq.pic.eoi = 0; qoriq.pic.whoami; } else { bsp_interrupt_handler_default(vector); } }
static int ppc_clock_exception_handler_e300( BSP_Exception_frame *frame, unsigned number) { uint32_t msr; /* Increment clock ticks */ Clock_driver_ticks += 1; /* Enable external exceptions */ msr = ppc_external_exceptions_enable(); /* Call clock ticker */ ppc_clock_tick(); /* Restore machine state */ ppc_external_exceptions_disable( msr); return 0; }
static int qoriq_external_exception_handler(BSP_Exception_frame *frame, unsigned exception_number) { rtems_vector_number vector = qoriq.pic.iack; if (vector != SPURIOUS) { uint32_t msr = ppc_external_exceptions_enable(); bsp_interrupt_handler_dispatch(vector); ppc_external_exceptions_disable(msr); qoriq.pic.eoi = 0; qoriq.pic.whoami; } else { bsp_interrupt_handler_default(vector); } return 0; }
static int ppc_clock_exception_handler( BSP_Exception_frame *frame, unsigned number ) { uint32_t delta = ppc_clock_decrementer_value; uint32_t next = ppc_clock_next_time_base; uint32_t dec = 0; uint32_t now = 0; uint32_t msr = 0; do { /* Increment clock ticks */ Clock_driver_ticks += 1; /* Enable external exceptions */ msr = ppc_external_exceptions_enable(); /* Call clock ticker */ ppc_clock_tick(); /* Restore machine state */ ppc_external_exceptions_disable( msr); /* Next time base */ next += delta; /* Current time */ now = ppc_time_base(); /* New decrementer value */ dec = next - now; } while (dec > delta); /* Set decrementer */ ppc_set_decrementer_register( dec); /* Expected next time base */ ppc_clock_next_time_base = next; return 0; }
static int ppc_clock_exception_handler_booke( BSP_Exception_frame *frame, unsigned number) { uint32_t msr; /* Acknowledge decrementer request */ PPC_SET_SPECIAL_PURPOSE_REGISTER( BOOKE_TSR, BOOKE_TSR_DIS); /* Increment clock ticks */ Clock_driver_ticks += 1; /* Enable external exceptions */ msr = ppc_external_exceptions_enable(); /* Call clock ticker */ ppc_clock_tick(); /* Restore machine state */ ppc_external_exceptions_disable( msr); return 0; }
/* * IRQ Handler: this is called from the primary exception dispatcher */ static int BSP_irq_handle_at_ipic( unsigned excNum) { int32_t vecnum; mpc83xx_ipic_mask_t mask_save; const mpc83xx_ipic_mask_t *mask_ptr; uint32_t msr = 0; rtems_interrupt_level level; /* Get vector number */ switch (excNum) { case ASM_EXT_VECTOR: vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.sivcr); break; case ASM_E300_SYSMGMT_VECTOR: vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.smvcr); break; case ASM_E300_CRIT_VECTOR: vecnum = MPC83xx_VCR_TO_VEC( mpc83xx.ipic.scvcr); break; default: return 1; } /* * Check the vector number, mask lower priority interrupts, enable * exceptions and dispatch the handler. */ if (MPC83XX_IPIC_IS_VALID_VECTOR( vecnum)) { #ifdef GEN83XX_ENABLE_INTERRUPT_NESTING mask_ptr = &mpc83xx_ipic_prio2mask [vecnum]; rtems_interrupt_disable( level); /* Save current mask registers */ mask_save.simsr_mask [0] = mpc83xx.ipic.simsr [0]; mask_save.simsr_mask [1] = mpc83xx.ipic.simsr [1]; mask_save.semsr_mask = mpc83xx.ipic.semsr; mask_save.sermr_mask = mpc83xx.ipic.sermr; /* Mask all lower priority interrupts */ mpc83xx.ipic.simsr [0] &= mask_ptr->simsr_mask [0]; mpc83xx.ipic.simsr [1] &= mask_ptr->simsr_mask [1]; mpc83xx.ipic.semsr &= mask_ptr->semsr_mask; mpc83xx.ipic.sermr &= mask_ptr->sermr_mask; rtems_interrupt_enable( level); /* Enable all interrupts */ if (excNum != ASM_E300_CRIT_VECTOR) { msr = ppc_external_exceptions_enable(); } #endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */ /* Dispatch interrupt handlers */ bsp_interrupt_handler_dispatch( vecnum + BSP_IPIC_IRQ_LOWEST_OFFSET); #ifdef GEN83XX_ENABLE_INTERRUPT_NESTING /* Restore machine state */ if (excNum != ASM_E300_CRIT_VECTOR) { ppc_external_exceptions_disable( msr); } /* Restore initial masks */ rtems_interrupt_disable( level); mpc83xx.ipic.simsr [0] = mask_save.simsr_mask [0]; mpc83xx.ipic.simsr [1] = mask_save.simsr_mask [1]; mpc83xx.ipic.semsr = mask_save.semsr_mask; mpc83xx.ipic.sermr = mask_save.sermr_mask; rtems_interrupt_enable( level); #endif /* GEN83XX_ENABLE_INTERRUPT_NESTING */ } else { bsp_interrupt_handler_default( vecnum); } return 0; }