int trap_handler(struct trapframe *tf) { switch(tf->trapno) { case TRAP_SYSCALL: print_tf(tf); return kern_syscall(tf->regs.eax, tf->regs.edx, tf->regs.ecx); case TRAP_GEP: // 2018-05-18 FIXME: found #GEP issue on vmware player 12.5.9 by testing print_tf(tf); panic("panic: system halt, not fix yet\n"); case TRAP_QEMU_MOUSE_CLICK: // not handle yet // [fixed] got 44 trap_handler while mouse click the window of qemu at the first time // after qemu-system-x86_64 started (tested in QEMU version 2.12.0, OSX 10.13.4) { unsigned char m_char = inb(0x60); printf("event mouse grap qemu window trapno(%d) eax: %04x, edx: %04x, ecx: %04x, mb:%02x\n", tf->trapno, tf->regs.eax, tf->regs.edx, tf->regs.ecx, m_char); } return 0; default: print_tf(tf); panic("panic: system halt\n"); } return 0; }
static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8_t registered, uint8_t voltage, uint16_t freq) { /* FIXME * Mainboards need to be able to specify the maximum number of DIMMs installable per channel * For now assume a maximum of 2 DIMMs per channel can be installed */ uint8_t MaxDimmsInstallable = 2; /* Return limited maximum RAM frequency */ if (IS_ENABLED(CONFIG_DIMM_DDR2)) { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { /* K10 BKDG Rev. 3.62 Table 53 */ if (count > 2) { /* Limit to DDR2-533 */ if (freq > 266) { freq = 266; print_tf(__func__, ": More than 2 registered DIMMs on channel; limiting to DDR2-533\n"); } } } else { /* K10 BKDG Rev. 3.62 Table 52 */ if (count > 1) { /* Limit to DDR2-800 */ if (freq > 400) { freq = 400; print_tf(__func__, ": More than 1 unbuffered DIMM on channel; limiting to DDR2-800\n"); } } } } else if (IS_ENABLED(CONFIG_DIMM_DDR3)) { if (voltage == 0) { printk(BIOS_DEBUG, "%s: WARNING: Mainboard DDR3 voltage unknown, assuming 1.5V!\n", __func__); voltage = 0x1; } if (is_fam15h()) { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { /* Fam15h BKDG Rev. 3.14 Table 27 */ if (voltage & 0x4) { /* 1.25V */ if (count > 1) { if (highest_rank_count > 1) { /* Limit to DDR3-1066 */ if (freq > 533) { freq = 533; printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } else if (voltage & 0x2) { /* 1.35V */ if (count > 1) { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } } else if (voltage & 0x1) { /* 1.50V */ if (count > 1) { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: More than 1 registered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1866 */ if (freq > 933) { freq = 933; printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); } } } } else { /* Fam15h BKDG Rev. 3.14 Table 26 */ if (voltage & 0x4) { /* 1.25V */ if (count > 1) { if (highest_rank_count > 1) { /* Limit to DDR3-1066 */ if (freq > 533) { freq = 533; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } else if (voltage & 0x2) { /* 1.35V */ if (MaxDimmsInstallable > 1) { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } } else if (voltage & 0x1) { if (MaxDimmsInstallable == 1) { if (count > 1) { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1866 */ if (freq > 933) { freq = 933; printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1866\n", __func__, voltage_index_to_mv(voltage)); } } } else { if (count > 1) { if (highest_rank_count > 1) { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: More than 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } } else { /* Limit to DDR3-1600 */ if (freq > 800) { freq = 800; printk(BIOS_DEBUG, "%s: 1 unbuffered DIMM on %dmV channel; limiting to DDR3-1600\n", __func__, voltage_index_to_mv(voltage)); } } } } } } else { if (IS_ENABLED(CONFIG_DIMM_REGISTERED) && registered) { /* K10 BKDG Rev. 3.62 Table 34 */ if (count > 2) { /* Limit to DDR3-800 */ if (freq > 400) { freq = 400; printk(BIOS_DEBUG, "%s: More than 2 registered DIMMs on %dmV channel; limiting to DDR3-800\n", __func__, voltage_index_to_mv(voltage)); } } else if (count == 2) { /* Limit to DDR3-1066 */ if (freq > 533) { freq = 533; printk(BIOS_DEBUG, "%s: 2 registered DIMMs on %dmV channel; limiting to DDR3-1066\n", __func__, voltage_index_to_mv(voltage)); } } else { /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: 1 registered DIMM on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } else { /* K10 BKDG Rev. 3.62 Table 33 */ /* Limit to DDR3-1333 */ if (freq > 666) { freq = 666; printk(BIOS_DEBUG, "%s: unbuffered DIMMs on %dmV channel; limiting to DDR3-1333\n", __func__, voltage_index_to_mv(voltage)); } } } } return freq; }