static uint32_t privateCSComputeCLKFrequency(uint16_t CLKSource, uint16_t CLKSourceDivider) { uint32_t CLKFrequency = 0; uint8_t CLKSourceFrequencyDivider = 1; CLKSourceFrequencyDivider = 1 << CLKSourceDivider; switch(CLKSource) { case SELMS__XT1CLK: CLKFrequency = (privateXT1ClockFrequency / CLKSourceFrequencyDivider); if(XTS != (HWREG16(CS_BASE + OFS_CSCTL6) & XTS)) { if(HWREG8(CS_BASE + OFS_CSCTL7) & XT1OFFG) { HWREG8(CS_BASE + OFS_CSCTL7) &= ~(XT1OFFG); //Clear OFIFG fault flag HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; if(HWREG8(CS_BASE + OFS_CSCTL7) & XT1OFFG) { CLKFrequency = CS_REFOCLK_FREQUENCY; } } } break; case SELMS__VLOCLK: CLKFrequency = (CS_VLOCLK_FREQUENCY / CLKSourceFrequencyDivider); break; case SELMS__REFOCLK: CLKFrequency = (CS_REFOCLK_FREQUENCY / CLKSourceFrequencyDivider); break; case SELMS__DCOCLKDIV: CLKFrequency = privateCSSourceClockFromDCO(CLKSource) / CLKSourceFrequencyDivider; break; } return (CLKFrequency); }
static uint32_t privateCSComputeCLKFrequency(uint16_t CLKSource, uint16_t CLKSourceDivider) { uint32_t CLKFrequency = 0; uint8_t CLKSourceFrequencyDivider = 1; uint8_t i = 0; // Determine Frequency divider for(i = 0; i < CLKSourceDivider; i++) { CLKSourceFrequencyDivider *= 2; } //Unlock CS control register HWREG16(CS_BASE + OFS_CSCTL0) = CSKEY; // Determine clock source based on CLKSource switch(CLKSource) { // If XT1 is selected as clock source case SELM__XT1CLK: CLKFrequency = (privateXT1ClockFrequency / CLKSourceFrequencyDivider); //Check if XT1OFFG is not set. If fault flag is set //VLO is used as source clock if(HWREG8(CS_BASE + OFS_CSCTL5) & XT1OFFG) { HWREG8(CS_BASE + OFS_CSCTL5) &= ~(XT1OFFG); //Clear OFIFG fault flag HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; if(HWREG8(CS_BASE + OFS_CSCTL5) & XT1OFFG) { CLKFrequency = CS_VLOCLK_FREQUENCY; } } break; case SELM__VLOCLK: CLKFrequency = (CS_VLOCLK_FREQUENCY / CLKSourceFrequencyDivider); break; case SELM__DCOCLK: CLKFrequency = privateCSSourceClockFromDCO(CLKSourceFrequencyDivider); break; case SELM__XT2CLK: CLKFrequency = (privateXT2ClockFrequency / CLKSourceFrequencyDivider); if(HWREG8(CS_BASE + OFS_CSCTL5) & XT2OFFG) { HWREG8(CS_BASE + OFS_CSCTL5) &= ~XT2OFFG; //Clear OFIFG fault flag HWREG8(SFR_BASE + OFS_SFRIFG1) &= ~OFIFG; } if(HWREG8(CS_BASE + OFS_CSCTL5) & XT2OFFG) { CLKFrequency = CS_MODCLK_FREQUENCY; } break; } // Lock CS control register HWREG8(CS_BASE + OFS_CSCTL0_H) = 0x00; return (CLKFrequency); }