/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode)
{
s16 prcm_offs;
omap2_clk_prepare_for_reboot();
set_and_lock_opps_max(true);
if (cpu_is_omap24xx())
prcm_offs = WKUP_MOD;
else if (cpu_is_omap34xx()) {
u32 l;
prcm_offs = OMAP3430_GR_MOD;
l = ('B' << 24) | ('M' << 16) | mode;
/* Reserve the first word in scratchpad for communicating
* with the boot ROM. A pointer to a data structure
* describing the boot process can be stored there,
* cf. OMAP34xx TRM, Initialization / Software Booting
* Configuration. */
omap_writel(l, OMAP343X_SCRATCHPAD + 4);
} else
WARN_ON(1);
#if defined(CONFIG_MACH_SHOLES) || defined(CONFIG_MACH_MAPPHONE)
prm_set_mod_reg_bits(OMAP_RST_GS, prcm_offs, RM_RSTCTRL);
#else
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
#endif
}
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode, const char *cmd)
{
s16 prcm_offs = 0;
if (cpu_is_omap24xx()) {
omap2xxx_clk_prepare_for_reboot();
prcm_offs = WKUP_MOD;
} else if (cpu_is_omap34xx()) {
u32 l;
prcm_offs = OMAP3430_GR_MOD;
l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0);
/* Reserve the first word in scratchpad for communicating
* with the boot ROM. A pointer to a data structure
* describing the boot process can be stored there,
* cf. OMAP34xx TRM, Initialization / Software Booting
* Configuration. */
omap_writel(l, OMAP343X_SCRATCHPAD + 4);
} else if (cpu_is_omap44xx())
prcm_offs = OMAP4430_PRM_DEVICE_MOD;
else
WARN_ON(1);
if (cpu_is_omap24xx() || cpu_is_omap34xx())
prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
OMAP2_RM_RSTCTRL);
if (cpu_is_omap44xx())
prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
prcm_offs, OMAP4_RM_RSTCTRL);
}
static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
const char *buf, size_t n)
{
unsigned short value;
if (sscanf(buf, "%hu", &value) != 1 ||
(value != 0 && value != 1)) {
printk(KERN_ERR "idle_store: Invalid value\n");
return -EINVAL;
}
if (attr == &sleep_while_idle_attr) {
enable_dyn_sleep = value;
} else if (attr == &clocks_off_while_idle_attr) {
clocks_off_while_idle = value;
} else if (attr == &enable_off_mode_attr) {
enable_off_mode = value;
omap3_pm_off_mode_enable(enable_off_mode);
} else if (attr == &voltage_off_while_idle_attr) {
voltage_off_while_idle = value;
if (voltage_off_while_idle)
prm_set_mod_reg_bits(OMAP3430_SEL_OFF, OMAP3430_GR_MOD,
OMAP3_PRM_VOLTCTRL_OFFSET);
else
prm_clear_mod_reg_bits(OMAP3430_SEL_OFF,
OMAP3430_GR_MOD,
OMAP3_PRM_VOLTCTRL_OFFSET);
} else {
return -EINVAL;
}
return n;
}
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode)
{
s16 prcm_offs;
omap2_clk_prepare_for_reboot();
if (cpu_is_omap24xx()) {
prcm_offs = WKUP_MOD;
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
} else if (cpu_is_omap34xx()) {
u32 l;
prcm_offs = OMAP3430_GR_MOD;
l = ('B' << 24) | ('M' << 16) | mode;
/* Reserve the first word in scratchpad for communicating
* with the boot ROM. A pointer to a data structure
* describing the boot process can be stored there,
* cf. OMAP34xx TRM, Initialization / Software Booting
* Configuration. */
omap_writel(l, OMAP343X_SCRATCHPAD + 4);
omap3_configure_core_dpll_warmreset();
} else
WARN_ON(1);
}
void pm_init_serial_console(void)
{
const struct omap_serial_console_config *conf;
char name[16];
conf = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
struct omap_serial_console_config);
if (conf == NULL)
return;
if (conf->console_uart > 3 || conf->console_uart < 1)
return;
serial_console_uart = conf->console_uart;
sprintf(name, "uart%d_fck", conf->console_uart);
console_fclk = clk_get(NULL, name);
if (IS_ERR(console_fclk))
console_fclk = NULL;
name[6] = 'i';
console_iclk = clk_get(NULL, name);
if (IS_ERR(console_fclk))
console_iclk = NULL;
if (console_fclk == NULL || console_iclk == NULL) {
serial_console_uart = 0;
return;
}
switch (serial_console_uart) {
case 1:
prm_set_mod_reg_bits(OMAP24XX_ST_UART1_MASK, CORE_MOD,
PM_WKEN1);
break;
case 2:
prm_set_mod_reg_bits(OMAP24XX_ST_UART2_MASK, CORE_MOD,
PM_WKEN1);
break;
case 3:
prm_set_mod_reg_bits(OMAP24XX_ST_UART3_MASK, CORE_MOD,
OMAP24XX_PM_WKEN2);
break;
}
}
/*
* Clears the scratchpad contents in case of cold boot-
* called during bootup
*/
void omap3_clear_scratchpad_contents(void)
{
u32 max_offset = OMAP343X_SCRATCHPAD_ROM_OFFSET;
u32 *v_addr;
u32 offset = 0;
v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM);
if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) &
OMAP3430_GLOBAL_COLD_RST) {
for ( ; offset <= max_offset; offset += 0x4)
__raw_writel(0x0, (v_addr + offset));
prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST, OMAP3430_GR_MOD,
OMAP3_PRM_RSTST_OFFSET);
}
}
static void omap3_enable_io_chain(void)
{
int timeout = 0;
if (omap_rev() >= OMAP3430_REV_ES3_1) {
prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
PM_WKEN);
/* Do a readback to assure write has been done */
prm_read_mod_reg(WKUP_MOD, PM_WKEN);
while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
OMAP3430_ST_IO_CHAIN_MASK)) {
timeout++;
if (timeout > 1000) {
printk(KERN_ERR "Wake up daisy chain "
"activation failed.\n");
return;
}
prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
WKUP_MOD, PM_WKEN);
}
}
}
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode)
{
#ifdef CONFIG_OMAP3_PM
omap_prcm_arch_pm_reset(mode);
#else
s16 prcm_offs;
if (cpu_is_omap24xx())
prcm_offs = WKUP_MOD;
else if (cpu_is_omap34xx())
prcm_offs = OMAP3430_GR_MOD;
else
WARN_ON(1);
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
#endif
}
/* Resets clock rates and reboots the system. Only called from system.h */
void omap_prcm_arch_reset(char mode, const char *cmd)
{
s16 prcm_offs;
omap2_clk_prepare_for_reboot();
if (cpu_is_omap24xx()) {
prcm_offs = WKUP_MOD;
prm_set_mod_reg_bits(OMAP_RST_DPLL3, prcm_offs, RM_RSTCTRL);
} else if (cpu_is_omap34xx()) {
u32 l;
/* Copy cmd into scratchpad memmory if any */
if(cmd != 0)
{
u16 counter = 0;
while((counter < (OMAP343X_SCRATCHPAD_BCB_SIZE-1)) && (cmd[counter]!='\0')) {
omap_writeb(cmd[counter], OMAP343X_SCRATCHPAD_BCB + counter);
counter++;
}
omap_writeb('\0', OMAP343X_SCRATCHPAD_BCB + counter);
}
prcm_offs = OMAP3430_GR_MOD;
l = ('B' << 24) | ('M' << 16) | mode;
/* Reserve the first word in scratchpad for communicating
* with the boot ROM. A pointer to a data structure
* describing the boot process can be stored there,
* cf. OMAP34xx TRM, Initialization / Software Booting
* Configuration. */
omap_writel(l, OMAP343X_SCRATCHPAD + 4);
omap3_configure_core_dpll_warmreset();
} else
WARN_ON(1);
}
