// Called when a vendor command is received
//
uint8 handleVendorCommand(uint8 cmd) {
if (handleUVCCommand(cmd))
return true;
if (handleCDCCommand(cmd))
return true;
switch(cmd) {
// Set various mode bits, or fetch status information
//
case CMD_MODE_STATUS:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
const __xdata uint16 param = SETUP_VALUE();
const __xdata uint8 value = SETUPDAT[4];
if ( param == FIFO_MODE ) {
// Enable or disable FIFO mode
fifoSetEnabled(value);
} else {
return false;
}
} else {
// Get STATUS: return the diagnostic byte
while ( EP0CS & bmEPBUSY );
EP0BUF[0] = 'N'; // Magic bytes (my cat's name)
EP0BUF[1] = 'E';
EP0BUF[2] = 'M';
EP0BUF[3] = 'I';
EP0BUF[4] = m_diagnosticCode; // Last operation diagnostic code
EP0BUF[5] = (IOA & bmBIT2) ? 0 : 1; // Flags
EP0BUF[6] = 0x11; // NeroProg endpoints
EP0BUF[7] = 0x26; // CommFPGA endpoints
EP0BUF[8] = 0xFF; // Firmware ID MSB
EP0BUF[9] = 0xFF; // Firmware ID LSB
EP0BUF[10] = (uint8)(DATE>>24); // Version MSB
EP0BUF[11] = (uint8)(DATE>>16); // Version
EP0BUF[12] = (uint8)(DATE>>8); // Version
EP0BUF[13] = (uint8)DATE; // Version LSB
EP0BUF[14] = 0x00; // Reserved
EP0BUF[15] = 0x00; // Reserved
// Return status packet to host
EP0BCH = 0;
SYNCDELAY;
EP0BCL = 16;
}
return true;
// Clock data into and out of the JTAG chain. Reads from EP2OUT and writes to EP4IN.
//
case CMD_PROG_CLOCK_DATA:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
EP0BCL = 0x00; // Allow host transfer in
while ( EP0CS & bmEPBUSY ); // Wait for data
progShiftBegin(*((uint32 *)EP0BUF), (ProgOp)SETUPDAT[4], SETUPDAT[2]); // Init numBits & flagByte
return true;
// Now that numBits & flagByte are set, this operation will continue in mainLoop()...
}
break;
// Clock an (up to) 32-bit pattern LSB-first into TMS to change JTAG TAP states
//
case CMD_JTAG_CLOCK_FSM:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
EP0BCL = 0x00; // Allow host transfer in
while ( EP0CS & bmEPBUSY ); // Wait for data
progClockFSM(*((uint32 *)EP0BUF), SETUPDAT[2]); // Bit pattern, transitionCount
return true;
}
break;
// Execute a number of JTAG clocks.
//
case CMD_JTAG_CLOCK:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
progClocks(*((uint32 *)(SETUPDAT+2)));
return true;
}
break;
// Set various mode bits, or fetch status information
//
case CMD_PORT_BIT_IO:
if ( SETUP_TYPE == (REQDIR_DEVICETOHOST | REQTYPE_VENDOR) ) {
const __xdata uint8 portNumber = SETUPDAT[2];
const __xdata uint8 bitNumber = SETUPDAT[3];
const __xdata uint8 drive = SETUPDAT[4];
const __xdata uint8 high = SETUPDAT[5];
if ( portNumber > 4 || bitNumber > 7 ) {
return false; // illegal port or bit
}
// Get the state of the port lines:
while ( EP0CS & bmEPBUSY );
EP0BUF[0] = portAccess(portNumber, (1<<bitNumber), drive, high);
EP0BCH = 0;
SYNCDELAY;
EP0BCL = 1;
return true;
}
break;
case CMD_PORT_MAP:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
__xdata uint8 patchClass = SETUPDAT[4];
const __xdata uint8 patchPort = SETUPDAT[5];
if ( patchClass == 0x00 ) {
// Patch class zero is just an anchor for the less flexible Harvard architecture
// micros like the AVR; since the FX2LP has a Von Neumann architecture it can
// efficiently self-modify its code, so the port mapping can be done individually,
// so there's no need for an anchor to group mapping operations together.
return true;
}
patchClass--;
if ( patchClass < 4 ) {
const __xdata uint8 patchBit = SETUPDAT[2];
livePatch(patchClass, 0x80 + (patchPort << 4) + patchBit);
} else {
livePatch(
patchClass,
0x80 + (patchPort << 4)
);
}
return true;
}
break;
// Command to talk to the EEPROM
//
case CMD_READ_WRITE_EEPROM:
if ( SETUP_TYPE == (REQDIR_DEVICETOHOST | REQTYPE_VENDOR) ) {
// It's an IN operation - read from prom and send to host
__xdata uint16 address = SETUP_VALUE();
__xdata uint16 length = SETUP_LENGTH();
__xdata uint16 chunkSize;
__xdata uint8 i;
while ( length ) {
while ( EP0CS & bmEPBUSY );
chunkSize = length < EP0BUF_SIZE ? length : EP0BUF_SIZE;
for ( i = 0; i < chunkSize; i++ ) {
EP0BUF[i] = 0x23;
}
promRead(SETUPDAT[4], address, chunkSize, EP0BUF);
EP0BCH = 0;
SYNCDELAY;
EP0BCL = chunkSize;
address += chunkSize;
length -= chunkSize;
}
} else if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
// It's an OUT operation - read from host and send to prom
__xdata uint16 address = SETUP_VALUE();
__xdata uint16 length = SETUP_LENGTH();
__xdata uint16 chunkSize;
while ( length ) {
EP0BCL = 0x00; // allow pc transfer in
while ( EP0CS & bmEPBUSY ); // wait for data
chunkSize = EP0BCL;
promWrite(SETUPDAT[4], address, chunkSize, EP0BUF);
address += chunkSize;
length -= chunkSize;
}
}
return true;
}
return false; // unrecognised command
}
// Called when a vendor command is received
//
uint8 handleVendorCommand(uint8 cmd) {
switch(cmd) {
// Set various mode bits, or fetch status information
//
case CMD_MODE_STATUS:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
xdata uint16 wBits = SETUP_VALUE();
xdata uint16 wMask = SETUP_INDEX();
if ( wMask & MODE_FIFO ) {
// Enable or disable FIFO mode
fifoSetEnabled(wBits & MODE_FIFO ? true : false);
} else {
return false;
}
} else {
// Get STATUS: return the diagnostic byte
while ( EP0CS & bmEPBUSY );
EP0BUF[0] = 'N'; // Magic bytes (my cat's name)
EP0BUF[1] = 'E';
EP0BUF[2] = 'M';
EP0BUF[3] = 'I';
EP0BUF[4] = m_diagnosticCode; // Last operation diagnostic code
EP0BUF[5] = (IOA & bmBIT2) ? 0 : 1; // Flags
EP0BUF[6] = 0x11; // NeroProg endpoints
EP0BUF[7] = 0x26; // CommFPGA endpoints
EP0BUF[8] = 0x00; // Reserved
EP0BUF[9] = 0x00; // Reserved
EP0BUF[10] = 0x00; // Reserved
EP0BUF[11] = 0x00; // Reserved
EP0BUF[12] = 0x00; // Reserved
EP0BUF[13] = 0x00; // Reserved
EP0BUF[14] = 0x00; // Reserved
EP0BUF[15] = 0x00; // Reserved
// Return status packet to host
EP0BCH = 0;
SYNCDELAY;
EP0BCL = 16;
}
return true;
// Clock data into and out of the JTAG chain. Reads from EP2OUT and writes to EP4IN.
//
case CMD_JTAG_CLOCK_DATA:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
EP0BCL = 0x00; // Allow host transfer in
while ( EP0CS & bmEPBUSY ); // Wait for data
progShiftBegin(*((uint32 *)EP0BUF), (ProgOp)SETUPDAT[4], SETUPDAT[2]); // Init numBits & flagByte
return true;
// Now that numBits & flagByte are set, this operation will continue in mainLoop()...
}
break;
// Clock an (up to) 32-bit pattern LSB-first into TMS to change JTAG TAP states
//
case CMD_JTAG_CLOCK_FSM:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
EP0BCL = 0x00; // Allow host transfer in
while ( EP0CS & bmEPBUSY ); // Wait for data
progClockFSM(*((uint32 *)EP0BUF), SETUPDAT[2]); // Bit pattern, transitionCount
return true;
}
break;
// Execute a number of JTAG clocks.
//
case CMD_JTAG_CLOCK:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
progClocks(*((uint32 *)(SETUPDAT+2)));
return true;
}
break;
// Set various mode bits, or fetch status information
//
case CMD_PORT_IO:
if ( SETUP_TYPE == (REQDIR_DEVICETOHOST | REQTYPE_VENDOR) ) {
const xdata uint8 portSelect = SETUPDAT[4];
const xdata uint8 mask = SETUPDAT[5];
xdata uint8 ddrWrite = SETUPDAT[2];
xdata uint8 portWrite = SETUPDAT[3];
//usartSendString("Got: ");
//usartSendByteHex(portSelect);
//usartSendByteHex(mask);
//usartSendByteHex(ddrWrite);
//usartSendByteHex(portWrite);
//usartSendByte('\r');
if ( portSelect > 4 ) {
return false; // illegal port
}
portWrite &= mask;
ddrWrite &= mask;
// Get the state of the port lines:
while ( EP0CS & bmEPBUSY );
EP0BUF[0] = portAccess(portSelect, mask, ddrWrite, portWrite);
EP0BCH = 0;
SYNCDELAY;
EP0BCL = 1;
return true;
}
break;
case CMD_PORT_MAP:
if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
const xdata uint8 patchClass = SETUPDAT[4];
const xdata uint8 patchPort = SETUPDAT[5];
if ( patchClass < 4 ) {
const xdata uint8 patchBit = SETUPDAT[2];
livePatch(patchClass, 0x80 + (patchPort << 4) + patchBit);
} else {
livePatch(
patchClass,
0x80 + (patchPort << 4)
);
}
return true;
}
break;
// Command to talk to the EEPROM
//
case CMD_READ_WRITE_EEPROM:
if ( SETUP_TYPE == (REQDIR_DEVICETOHOST | REQTYPE_VENDOR) ) {
// It's an IN operation - read from prom and send to host
xdata uint16 address = SETUP_VALUE();
xdata uint16 length = SETUP_LENGTH();
xdata uint16 chunkSize;
xdata uint8 i;
while ( length ) {
while ( EP0CS & bmEPBUSY );
chunkSize = length < EP0BUF_SIZE ? length : EP0BUF_SIZE;
for ( i = 0; i < chunkSize; i++ ) {
EP0BUF[i] = 0x23;
}
promRead(SETUPDAT[4], address, chunkSize, EP0BUF);
EP0BCH = 0;
SYNCDELAY;
EP0BCL = chunkSize;
address += chunkSize;
length -= chunkSize;
}
} else if ( SETUP_TYPE == (REQDIR_HOSTTODEVICE | REQTYPE_VENDOR) ) {
// It's an OUT operation - read from host and send to prom
xdata uint16 address = SETUP_VALUE();
xdata uint16 length = SETUP_LENGTH();
xdata uint16 chunkSize;
while ( length ) {
EP0BCL = 0x00; // allow pc transfer in
while ( EP0CS & bmEPBUSY ); // wait for data
chunkSize = EP0BCL;
promWrite(SETUPDAT[4], address, chunkSize, EP0BUF);
address += chunkSize;
length -= chunkSize;
}
}
return true;
}
return false; // unrecognised command
}