/*********************************************************************** * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ long int initdram (int board_type) { unsigned int dram_size = 0; mtsdram(DDR0_02, 0x00000000); /* Values must be kept in sync with Excel-table <<A0001492.>> ! */ mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030602); mtsdram(DDR0_04, 0x0A020200); mtsdram(DDR0_05, 0x02020307); switch (in_be16((u16 *)HCU_HW_VERSION_REGISTER) & HCU_HW_SDRAM_CONFIG_MASK) { case 1: dram_size = 256 * 1024 * 1024 ; mtsdram(DDR0_06, 0x0102C812); /* 256MB RAM */ mtsdram(DDR0_11, 0x0014C800); /* 256MB RAM */ mtsdram(DDR0_43, 0x030A0200); /* 256MB RAM */ break; case 0: default: dram_size = 128 * 1024 * 1024 ; mtsdram(DDR0_06, 0x0102C80D); /* 128MB RAM */ mtsdram(DDR0_11, 0x000FC800); /* 128MB RAM */ mtsdram(DDR0_43, 0x030A0300); /* 128MB RAM */ break; } mtsdram(DDR0_07, 0x00090100); /* * TCPD=200 cycles of clock input is required to lock the DLL. * CKE must be HIGH the entire time.mtsdram(DDR0_08, 0x02C80001); */ mtsdram(DDR0_08, 0x02C80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1D000000); mtsdram(DDR0_18, 0x1D1D1D1D); mtsdram(DDR0_19, 0x1D1D1D1D); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, ECC_RAM); #else mtsdram(DDR0_22, NO_ECC_RAM); #endif mtsdram(DDR0_23, 0x00000000); mtsdram(DDR0_24, 0x01020001); mtsdram(DDR0_26, 0x2D930517); mtsdram(DDR0_27, 0x00008236); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000006); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); wait_for_dlllock(); mtsdram(DDR0_00, 0x40000000); /* Zero init bit */ /* * Program tlb entries for this size (dynamic) */ remove_tlb(CFG_SDRAM_BASE, 256 << 20); program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual * address with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0); #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CFG_DDR_CACHED_ADDR, dram_size); #endif return (dram_size); }
/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ phys_size_t initdram (int board_type) { #if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_LCD4_LWMON5) /* CL=4 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ mtsdram(DDR0_04, 0x0B030300); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0003C812); mtsdram(DDR0_07, 0x00090100); mtsdram(DDR0_08, 0x03c80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000100); mtsdram(DDR0_11, 0x000CC800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1e000000); mtsdram(DDR0_18, 0x1e1e1e1e); mtsdram(DDR0_19, 0x1e1e1e1e); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ #else mtsdram(DDR0_22, 0x00267F0B); #endif mtsdram(DDR0_23, 0x01000000); mtsdram(DDR0_24, 0x01010001); mtsdram(DDR0_26, 0x2D93028A); mtsdram(DDR0_27, 0x0784682B); mtsdram(DDR0_28, 0x00000080); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000008); mtsdram(DDR0_43, 0x050A0200); mtsdram(DDR0_44, 0x00000005); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ denali_wait_for_dlllock(); #if defined(CONFIG_DDR_DATA_EYE) /* -----------------------------------------------------------+ * Perform data eye search if requested. * ----------------------------------------------------------*/ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, TLB_WORD2_I_ENABLE); denali_core_search_data_eye(); remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* * Program tlb entries for this size (dynamic) */ program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); #if defined(CONFIG_DDR_ECC) #if defined(CONFIG_4xx_DCACHE) /* * If ECC is enabled, initialize the parity bits. */ program_ecc(0, CONFIG_SYS_MBYTES_SDRAM << 20, 0); #else /* CONFIG_4xx_DCACHE */ /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0); /* * Now after initialization (auto-calibration and ECC generation) * remove the TLB entries with caches enabled and program again with * desired cache functionality */ remove_tlb(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20); #endif /* CONFIG_4xx_DCACHE */ #endif /* CONFIG_DDR_ECC */ /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); #endif /* CONFIG_SPL_BUILD */ return (CONFIG_SYS_MBYTES_SDRAM << 20); }
/************************************************************************* * * initdram -- 440EPx's DDR controller is a DENALI Core * ************************************************************************/ long int initdram (int board_type) { #if 0 /* test-only: will remove this define later, when ECC problems are solved! */ /* CL=3 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */ mtsdram(DDR0_04, 0x0A030300); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0103C812); mtsdram(DDR0_07, 0x00090100); mtsdram(DDR0_08, 0x02c80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000300); mtsdram(DDR0_11, 0x000CC800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1e000000); mtsdram(DDR0_18, 0x1e1e1e1e); mtsdram(DDR0_19, 0x1e1e1e1e); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ #else mtsdram(DDR0_22, 0x00267F0B); #endif mtsdram(DDR0_23, 0x01000000); mtsdram(DDR0_24, 0x01010001); mtsdram(DDR0_26, 0x2D93028A); mtsdram(DDR0_27, 0x0784682B); mtsdram(DDR0_28, 0x00000080); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000006); mtsdram(DDR0_43, 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ #else /* CL=4 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); mtsdram(DDR0_01, 0x01000000); mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ mtsdram(DDR0_04, 0x0B030300); mtsdram(DDR0_05, 0x02020308); mtsdram(DDR0_06, 0x0003C812); mtsdram(DDR0_07, 0x00090100); mtsdram(DDR0_08, 0x03c80001); mtsdram(DDR0_09, 0x00011D5F); mtsdram(DDR0_10, 0x00000300); mtsdram(DDR0_11, 0x000CC800); mtsdram(DDR0_12, 0x00000003); mtsdram(DDR0_14, 0x00000000); mtsdram(DDR0_17, 0x1e000000); mtsdram(DDR0_18, 0x1e1e1e1e); mtsdram(DDR0_19, 0x1e1e1e1e); mtsdram(DDR0_20, 0x0B0B0B0B); mtsdram(DDR0_21, 0x0B0B0B0B); #ifdef CONFIG_DDR_ECC mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ #else mtsdram(DDR0_22, 0x00267F0B); #endif mtsdram(DDR0_23, 0x01000000); mtsdram(DDR0_24, 0x01010001); mtsdram(DDR0_26, 0x2D93028A); mtsdram(DDR0_27, 0x0784682B); mtsdram(DDR0_28, 0x00000080); mtsdram(DDR0_31, 0x00000000); mtsdram(DDR0_42, 0x01000008); mtsdram(DDR0_43, 0x050A0200); mtsdram(DDR0_44, 0x00000005); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ #endif wait_for_dlllock(); /* * Program tlb entries for this size (dynamic) */ program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE); /* * Setup 2nd TLB with same physical address but different virtual address * with cache enabled. This is done for fast ECC generation. */ program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); #ifdef CONFIG_DDR_DATA_EYE /* * Perform data eye search if requested. */ denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20); #endif #ifdef CONFIG_DDR_ECC /* * If ECC is enabled, initialize the parity bits. */ program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0); #endif /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); return (CFG_MBYTES_SDRAM << 20); }