static int ep93xx_devices_init(void)
{
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x60000000, EDB93XX_CFI_FLASH_SIZE, 0);
/*
* Create partitions that should be
* not touched by any regular user
*/
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 6, data width is 16 bit
*/
add_generic_device("ep93xx_eth", DEVICE_ID_DYNAMIC, NULL, 0, 0, IORESOURCE_MEM,
NULL);
armlinux_set_bootparams((void *)CONFIG_EP93XX_SDRAM_BANK0_BASE + 0x100);
armlinux_set_architecture(MACH_TYPE);
return 0;
}
static int scb9328_devices_init(void) {
imx_gpio_mode(PA23_PF_CS5);
/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
FMCR = 0x1;
CS0U = 0x000F2000;
CS0L = 0x11110d01;
CS1U = 0x000F0a00;
CS1L = 0x11110601;
CS2U = 0x0;
CS2L = 0x0;
CS3U = 0x000FFFFF;
CS3L = 0x00000303;
CS4U = 0x000F0a00;
CS4L = 0x11110301;
CS5U = 0x00008400;
CS5L = 0x00000D03;
register_device(&cfi_dev);
register_device(&sdram_dev);
register_device(&dm9000_dev);
devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0x08000100);
armlinux_set_architecture(MACH_TYPE_SCB9328);
return 0;
}
static int scb9328_devices_init(void)
{
int i;
imx_gpio_mode(PA23_PF_CS5);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 21);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 22);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 23);
imx_gpio_mode(GPIO_PORTB | GPIO_GPIO | GPIO_OUT | 24);
for (i = 0; i < ARRAY_SIZE(leds); i++)
led_gpio_register(&leds[i]);
/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
writel(0x1, MX1_SCM_BASE_ADDR + MX1_FMCR);
imx1_setup_eimcs(0, 0x000F2000, 0x11110d01);
imx1_setup_eimcs(1, 0x000F0a00, 0x11110601);
imx1_setup_eimcs(3, 0x000FFFFF, 0x00000303);
imx1_setup_eimcs(4, 0x000F0a00, 0x11110301);
imx1_setup_eimcs(5, 0x00008400, 0x00000D03);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0x10000000, 16 * 1024 * 1024, 0);
add_dm9000_device(DEVICE_ID_DYNAMIC, 0x16000000, 0x16000004,
IORESOURCE_MEM_16BIT, &dm9000_data);
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0x08000100);
armlinux_set_architecture(MACH_TYPE_SCB9328);
return 0;
}
static int pcm043_devices_init(void)
{
uint32_t reg;
char *envstr;
unsigned long bbu_nand_flags = 0;
/* CS0: Nor Flash */
imx35_setup_weimcs(5, 0x22C0CF00, 0x75000D01, 0x00000900);
led_gpio_register(&led0);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
imx35_add_fec(&fec_info);
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_add_partition("nand0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envstr = "NAND";
bbu_nand_flags = BBU_HANDLER_FLAG_DEFAULT;
break;
case BOOTSOURCE_NOR:
default:
devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", SZ_512K, SZ_128K, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
envstr = "NOR";
break;
}
pr_info("using environment from %s flash\n", envstr);
imx35_add_fb(&ipu_fb_data);
armlinux_set_architecture(MACH_TYPE_PCM043);
imx_bbu_external_nand_register_handler("nand", "/dev/nand0.barebox",
bbu_nand_flags);
return 0;
}
void* mmap(void* addr, size_t len, int prot, int flags, int fildes, oft__ off)
{
#ifdef _MSC_VER
#pragma warning(push)
#pragma warning(disable: 4293)
#endif
const DWORD access = protect_file(prot);
const DWORD protect = protect_page(prot);
const oft__ max = off + (oft__)len;
const DWORD max_lo = large ? (DWORD)((max) & MAXDWORD) : (DWORD)max;
const DWORD max_hi = large ? (DWORD)((max >> 32) & MAXDWORD) : (DWORD)0;
const DWORD file_lo = large ? (DWORD)((off) & MAXDWORD) : (DWORD)off;
const DWORD file_hi = large ? (DWORD)((off >> 32) & MAXDWORD) : (DWORD)0;
#ifdef _MSC_VER
#pragma warning(pop)
#endif
if (len == 0 || (flags & MAP_FIXED) != 0 || prot == PROT_EXEC)
{
errno = EINVAL;
return MAP_FAILED;
}
const HANDLE handle = ((flags & MAP_ANONYMOUS) == 0) ?
(HANDLE)_get_osfhandle(fildes) : INVALID_HANDLE_VALUE;
if ((flags & MAP_ANONYMOUS) == 0 && handle == INVALID_HANDLE_VALUE)
{
errno = EBADF;
return MAP_FAILED;
}
const HANDLE mapping = CreateFileMappingW(handle, NULL, protect, max_hi,
max_lo, NULL);
if (mapping == NULL)
{
errno = last_error(EPERM);
return MAP_FAILED;
}
const LPVOID map = MapViewOfFile(mapping, access, file_hi, file_lo, len);
/* TODO: verify mapping handle may be closed here and then use the map. */
if (map == NULL || CloseHandle(mapping) == FALSE)
{
errno = last_error(EPERM);
return MAP_FAILED;
}
errno = 0;
return map;
}
static int pcm037_devices_init(void)
{
/* CS0: Nor Flash */
imx31_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
/* CS1: Network Controller */
imx31_setup_weimcs(1, 0x0000df06, 0x444a4541, 0x44443302);
/* CS4: SRAM */
imx31_setup_weimcs(4, 0x0000d843, 0x22252521, 0x22220a00);
/* CS5: SJA1000 */
imx31_setup_weimcs(4, 0x0000DCF6, 0x444A0301, 0x44443302);
/*
* Up to 32MiB NOR type flash, connected to
* CS line 0, data width is 16 bit
*/
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX31_CS0_BASE_ADDR, 32 * 1024 * 1024, 0);
imx31_add_mmc0(NULL);
/*
* Create partitions that should be
* not touched by any regular user
*/
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0"); /* ourself */
devfs_add_partition("nor0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env0"); /* environment */
protect_file("/dev/env0", 1);
/*
* up to 2MiB static RAM type memory, connected
* to CS4, data width is 16 bit
*/
add_mem_device("sram0", MX31_CS4_BASE_ADDR, MX31_CS4_SIZE, /* area size */
IORESOURCE_MEM_WRITEABLE);
imx31_add_nand(&nand_info);
/*
* SMSC 9217 network controller
* connected to CS line 1 and interrupt line
* GPIO3, data width is 16 bit
*/
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX31_CS1_BASE_ADDR,
MX31_CS1_SIZE, IORESOURCE_MEM, &smsc9217_pdata);
#ifdef CONFIG_USB
pcm037_usb_init();
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_OTG_BASE_ADDR, NULL);
add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX31_USB_HS2_BASE_ADDR, NULL);
#endif
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_PCM037);
return 0;
}
static int f3s_devices_init(void)
{
uint32_t reg;
/* CS0: Nor Flash */
imx35_setup_weimcs(0, 0x0000cf03, 0x10000d03, 0x00720900);
reg = readl(MX35_CCM_BASE_ADDR + MX35_CCM_RCSR);
/* some fuses provide us vital information about connected hardware */
if (reg & 0x20000000)
nand_info.width = 2; /* 16 bit */
else
nand_info.width = 1; /* 8 bit */
/*
* This platform supports NOR and NAND
*/
imx35_add_nand(&nand_info);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, MX35_CS0_BASE_ADDR, 64 * 1024 * 1024, 0);
switch ((reg >> 25) & 0x3) {
case 0x01: /* NAND is the source */
devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
break;
case 0x00: /* NOR is the source */
devfs_add_partition("nor0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
break;
}
set_silicon_rev(imx_silicon_revision());
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
imx35_add_i2c0(NULL);
imx35_add_fec(&fec_info);
add_generic_device("smc911x", DEVICE_ID_DYNAMIC, NULL, MX35_CS5_BASE_ADDR, MX35_CS5_SIZE,
IORESOURCE_MEM, NULL);
imx35_add_mmc0(NULL);
imx35_add_fb(&ipu_fb_data);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_MX35_3DS);
return 0;
}
static int netx_devices_init(void) {
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, ð0_data);
add_generic_device("netx-eth", -1, NULL, 0, 0, IORESOURCE_MEM, ð1_data);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
/* Do not overwrite primary env for now */
devfs_add_partition("nor0", 0xc0000, 0x80000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0x80000100);
armlinux_set_architecture(MACH_TYPE_NXDB500);
return 0;
}
static int mx27ads_devices_init(void)
{
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
};
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_fec(&fec_info);
devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_MX27ADS);
return 0;
}
static int ipe337_devices_init(void) {
register_device(&cfi_dev);
register_device(&sdram_dev);
/* Reset smc911x */
*pFIO0_DIR = (1<<12);
*pFIO0_FLAG_C = (1<<12);
mdelay(100);
*pFIO0_FLAG_S = (1<<12);
register_device(&smc911x_dev);
devfs_add_partition("nor0", 0x00000, 0x20000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x20000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
return 0;
}
static int pcm027_devices_init(void)
{
void *cfi_iospace;
add_generic_device("smc91c111", DEVICE_ID_DYNAMIC, NULL, 0x14000300, 16,
IORESOURCE_MEM, NULL);
cfi_iospace = map_io_sections(0x0, (void *)0xe0000000, SZ_32M);
add_cfi_flash_device(DEVICE_ID_DYNAMIC, (unsigned long)cfi_iospace, SZ_32M, 0);
pxa_add_fb((void *)0x44000000, &fb_pdata);
armlinux_set_architecture(MACH_TYPE_PCM027);
devfs_add_partition("nor0", 0x00000, SZ_512K, DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", SZ_512K, SZ_256K, DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
return 0;
}
static int eukrea_cpuimx27_devices_init(void)
{
char *envdev = "no";
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
#ifdef CONFIG_DRIVER_SERIAL_IMX
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
#endif
#ifdef CONFIG_DRIVER_VIDEO_IMX
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA31_PF_OE_ACD,
GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT,
#endif
};
eukrea_cpuimx27_mmu_init();
/* configure 16 bit nor flash on cs0 */
CS0U = 0x00008F03;
CS0L = 0xA0330D01;
CS0A = 0x002208C0;
/* initialize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
register_device(&cfi_dev);
#ifdef CONFIG_EUKREA_CPUIMX27_NOR_64MB
register_device(&cfi_dev1);
#endif
register_device(&nand_dev);
register_device(&sdram_dev);
PCCR0 |= PCCR0_I2C1_EN;
i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));
register_device(&i2c_dev);
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
printf("Using environment in %s Flash\n", envdev);
#ifdef CONFIG_DRIVER_VIDEO_IMX
register_device(&imxfb_dev);
gpio_direction_output(GPIO_PORTE | 5, 0);
gpio_set_value(GPIO_PORTE | 5, 1);
#endif
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_CPUIMX27);
return 0;
}
static int pcm038_devices_init(void)
{
int i;
char *envdev;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
PD25_PF_CSPI1_RDY,
GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
/* display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB host 2 */
PA0_PF_USBH2_CLK,
PA1_PF_USBH2_DIR,
PA2_PF_USBH2_DATA7,
PA3_PF_USBH2_NXT,
PA4_PF_USBH2_STP,
PD19_AF_USBH2_DATA4,
PD20_AF_USBH2_DATA3,
PD21_AF_USBH2_DATA6,
PD22_AF_USBH2_DATA0,
PD23_AF_USBH2_DATA2,
PD24_AF_USBH2_DATA1,
PD26_AF_USBH2_DATA5,
};
pcm038_mmu_init();
/* configure 16 bit nor flash on cs0 */
CS0U = 0x0000CC03;
CS0L = 0xa0330D01;
CS0A = 0x00220800;
/* configure SRAM on cs1 */
CS1U = 0x0000d843;
CS1L = 0x22252521;
CS1A = 0x22220a00;
/* configure SJA1000 on cs4 */
CS4U = 0x0000DCF6;
CS4L = 0x444A0301;
CS4A = 0x44443302;
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
PCCR0 |= PCCR0_CSPI1_EN;
PCCR1 |= PCCR1_PERCLK2_EN;
gpio_direction_output(GPIO_PORTD | 28, 0);
gpio_set_value(GPIO_PORTD | 28, 0);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
register_device(&spi_dev);
register_device(&cfi_dev);
register_device(&nand_dev);
register_device(&sdram_dev);
register_device(&sram_dev);
register_device(&imxfb_dev);
#ifdef CONFIG_USB
pcm038_usbh_init();
register_device(&usbh2_dev);
#endif
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
register_device(&fec_dev);
switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
case GPCR_BOOT_8BIT_NAND_2k:
case GPCR_BOOT_16BIT_NAND_2k:
case GPCR_BOOT_16BIT_NAND_512:
case GPCR_BOOT_8BIT_NAND_512:
devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
}
printf("Using environment in %s Flash\n", envdev);
armlinux_add_dram(&sdram_dev);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}
static int pcm038_devices_init(void)
{
int i;
u64 uid = 0;
char *envdev;
long sram_size;
unsigned int mode[] = {
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT,
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* CSPI1 */
PD25_PF_CSPI1_RDY,
PD29_PF_CSPI1_SCLK,
PD30_PF_CSPI1_MISO,
PD31_PF_CSPI1_MOSI,
PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT,
#ifdef CONFIG_MACH_PCM970_BASEBOARD
PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT,
#endif
/* Display */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA24_PF_REV,
PA25_PF_CLS,
PA26_PF_PS,
PA27_PF_SPL_SPR,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
PA31_PF_OE_ACD,
/* USB OTG */
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* I2C1 */
PD17_PF_I2C_DATA | GPIO_PUEN,
PD18_PF_I2C_CLK,
/* I2C2 */
PC5_PF_I2C2_SDA,
PC6_PF_I2C2_SCL,
};
/* configure 16 bit nor flash on cs0 */
imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900);
/* configure SRAM on cs1 */
imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);
/* SRAM can be up to 2MiB */
sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M);
if (sram_size)
add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size,
IORESOURCE_MEM_WRITEABLE);
/* initizalize gpios */
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
imx27_add_spi0(&pcm038_spi_0_data);
pcm038_power_init();
add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
imx27_add_nand(&nand_info);
imx27_add_fb(&pcm038_fb_data);
imx27_add_i2c0(NULL);
imx27_add_i2c1(NULL);
/* Register the fec device after the PLL re-initialisation
* as the fec depends on the (now higher) ipg clock
*/
gpio_set_value(PCM038_GPIO_FEC_RST, 1);
imx27_add_fec(&fec_info);
/* Apply delay for STP line to stop ULPI */
gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
mdelay(1);
imx_gpio_mode(PE1_PF_USBOTG_STP);
imx27_add_usbotg(&pcm038_otg_pdata);
switch (bootsource_get()) {
case BOOTSOURCE_NAND:
devfs_add_partition("nand0", 0, SZ_512K,
DEVFS_PARTITION_FIXED, "self_raw");
dev_add_bb_dev("self_raw", "self0");
devfs_add_partition("nand0", SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env_raw");
dev_add_bb_dev("env_raw", "env0");
envdev = "NAND";
break;
default:
devfs_add_partition("nor0", 0, SZ_512K,
DEVFS_PARTITION_FIXED, "self0");
devfs_add_partition("nor0", SZ_512K, SZ_128K,
DEVFS_PARTITION_FIXED, "env0");
protect_file("/dev/env0", 1);
envdev = "NOR";
}
pr_notice("Using environment in %s Flash\n", envdev);
if (imx_iim_read(1, 0, &uid, 6) == 6)
armlinux_set_serial(uid);
armlinux_set_bootparams((void *)0xa0000100);
armlinux_set_architecture(MACH_TYPE_PCM038);
return 0;
}
