/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_logic_state_get
* @BRIEF return the current logic state of a given power domain
* @RETURNS current logic state on success
* PWRDM_STATE_MAX in case of error
* @param[in] powerdm: power domain name
* @DESCRIPTION return the current logic state of a given power domain
*//*------------------------------------------------------------------------ */
pwrdm_state powerdm_logic_state_get(const char *powerdm)
{
reg *pm_pwrstst;
pwrdm_state state;
CHECK_NULL_ARG(powerdm, PWRDM_STATE_MAX);
pm_pwrstst = powerdm_pwrstst_reg_get(powerdm);
if (pm_pwrstst == NULL) {
dprintf("%s(%s): PM_PWRSTST==NULL!\n", __func__, powerdm);
return PWRDM_STATE_MAX;
}
state = pwrdm_logic_state_get(pm_pwrstst);
dprintf("%s(%s) = %s\n", __func__, powerdm,
pwrdm_state_name_get(state));
return state;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_state_get
* @BRIEF return the previous/current/target state of
* a given power domain
* @RETURNS domain previous/current/target state on success
* PWRDM_STATE_MAX in case of error
* @param[in] powerdm: power domain name
* @param[in] type: power domain state type
* @DESCRIPTION return the previous/current/target state of
* a given power domain
*//*------------------------------------------------------------------------ */
pwrdm_state powerdm_state_get(const char *powerdm, pwrdm_state_type type)
{
reg *pm_reg;
pwrdm_state state;
CHECK_NULL_ARG(powerdm, PWRDM_STATE_MAX);
CHECK_ARG_LESS_THAN(type, PWRDM_STATE_TYPE_MAX, PWRDM_STATE_MAX);
/* Retrieve registers address */
switch (type) {
case PWRDM_STATE_TARGET:
pm_reg = powerdm_pwrstctrl_reg_get(powerdm);
break;
case PWRDM_STATE_CURRENT:
case PWRDM_STATE_PREVIOUS:
pm_reg = powerdm_pwrstst_reg_get(powerdm);
break;
default:
fprintf(stderr,
"omapconf: %s(%s): invalid type (%d)!\n",
__func__, powerdm, type);
return PWRDM_STATE_MAX;
}
if (pm_reg == NULL) {
/* Always ON domain */
dprintf("%s(%s): Always ON domain\n", __func__, powerdm);
return PWRDM_ON_STATE;
}
/* Retrieve power domain state */
state = pwrdm_state_get(pm_reg, type);
dprintf("%s(%s, %s) = %s\n", __func__, powerdm,
pwrdm_state_type_name_get(type),
pwrdm_state_name_get(state));
return state;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_target_logic_ret_state_get
* @BRIEF return the programmed target logic retention state
* of a given power domain
* @RETURNS programmed target logic retention state on success
* PWRDM_STATE_MAX in case of error
* @param[in] powerdm: power domain name
* @DESCRIPTION return the programmed target logic retention state
* of a given power domain
*//*------------------------------------------------------------------------ */
pwrdm_state powerdm_target_logic_ret_state_get(const char *powerdm)
{
reg *pm_pwrstctrl;
pwrdm_state state;
CHECK_NULL_ARG(powerdm, PWRDM_STATE_MAX);
if (!powerdm_has_logic_ret_state_ctrl_bit(powerdm)) {
dprintf("%s(%s): domain doesn't have RET state control bit.\n",
__func__, powerdm);
return PWRDM_STATE_MAX;
}
pm_pwrstctrl = powerdm_pwrstctrl_reg_get(powerdm);
if (pm_pwrstctrl == NULL) {
dprintf("%s(%s): PM_PWRSTCTRL==NULL!\n", __func__, powerdm);
return PWRDM_STATE_MAX;
}
state = pwrdm_target_logic_ret_state_get(pm_pwrstctrl);
dprintf("%s(%s) = %s\n", __func__, powerdm,
pwrdm_state_name_get(state));
return state;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION pwrdm54xx_config_show
* @BRIEF decode and display power domain configuration
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* @param[in,out] stream: output file
* @param[in] id: valid power domain ID
* @DESCRIPTION decode and display power domain configuration
*//*------------------------------------------------------------------------ */
int pwrdm54xx_config_show(FILE *stream, pwrdm54xx_id id)
{
pwrdm_state st_last, st_curr, st_tgt;
CHECK_CPU(54xx, OMAPCONF_ERR_CPU);
CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG);
CHECK_ARG_LESS_THAN(id, PWRDM54XX_ID_MAX, OMAPCONF_ERR_ARG);
char s1[32], s2[32];
reg *pm_pwrstctrl_reg;
reg *pm_pwrstst_reg;
unsigned int pm_pwrstctrl;
unsigned int pm_pwrstst;
char s[64];
fprintf(stream, "|---------------------------------------------------"
"-------------|\n");
strcpy(s, pwrdm54xx_name_get(id));
strcat(s, " Power Domain Configuration");
fprintf(stream, "| %-62s |\n", s);
fprintf(stream, "|---------------------------------------------------"
"-------------|\n");
fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Power State",
"Current", "Target", "Last");
fprintf(stream, "|----------------------------------|---------|------"
"---|---------|\n");
st_last = pwrdm54xx_state_get(id, PWRDM_STATE_PREVIOUS);
st_curr = pwrdm54xx_state_get(id, PWRDM_STATE_CURRENT);
st_tgt = pwrdm54xx_state_get(id, PWRDM_STATE_TARGET);
fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n",
"Domain", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt), pwrdm_state_name_get(st_last));
if ((!pwrdm54xx_has_logic_ret_state_ctrl_bit(id)) &&
(!pwrdm54xx_has_pwrstst_reg(id)))
goto pwrdm54xx_config_show_mem;
st_tgt = pwrdm54xx_target_logic_ret_state_get(id);
if (st_tgt != PWRDM_STATE_MAX)
strcpy(s1, pwrdm_state_name_get(st_tgt));
else
strcpy(s1, "");
st_curr = pwrdm54xx_logic_state_get(id);
if (st_curr != PWRDM_STATE_MAX)
strcpy(s2, pwrdm_state_name_get(st_curr));
else
strcpy(s2, "");
fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Logic", s2, s1);
pwrdm54xx_config_show_mem:
if (pwrdm54xx_has_pwrstctrl_reg(id)) {
pm_pwrstctrl_reg = pwrdm54xx_pwrstctrl_reg_get(id);
pm_pwrstctrl = reg_read(pm_pwrstctrl_reg);
}
if (pwrdm54xx_has_pwrstst_reg(id)) {
pm_pwrstst_reg = pwrdm54xx_pwrstst_reg_get(id);
pm_pwrstst = reg_read(pm_pwrstst_reg);
}
switch (id) {
case PWRDM54XX_EMU:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" EMU bank", pwrdm_state_name_get(st_curr), "");
break;
case PWRDM54XX_CAM:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" MEM", pwrdm_state_name_get(st_curr), "");
break;
case PWRDM54XX_CORE:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 12, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 12);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" OCP_WP/UNIPRO1/DMM bank2",
pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 10, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 11);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" IPU S$", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" IPU L2RAM", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" OCMRAM", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" DMA/ICR/DMM bank1", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_DSS:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2);
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" MEM", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_L3_INIT:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" L3INIT bank2", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" L3INIT bank1", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_L4_PER:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" NONRETAINED bank", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" RETAINED bank", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_ABE:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" AESS", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" PERIPH", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_DSP:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" EDMA", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" L2$", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" L1$", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_GPU:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" MEM", pwrdm_state_name_get(st_curr), "");
break;
case PWRDM54XX_IVA:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 10, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 11);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" TCM2", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 8, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 10);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" TCM1", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" SL2", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 4, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 8);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" HWA", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
case PWRDM54XX_MPU:
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
"Memory", "", "");
st_curr = (pwrdm_state) extract_bitfield(pm_pwrstst, 6, 2);
st_tgt = (pwrdm_state) extract_bit(pm_pwrstctrl, 9);
fprintf(stream, "| %-32s | %-7s | %-7s | |\n",
" L2$", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt));
break;
default:
/* Nothing to print */
break;
}
if (pwrdm54xx_has_pwrstst_reg(id)) {
fprintf(stream, "|---------------------------------------------"
"-------------------|\n");
fprintf(stream, "| %-32s | %-27s |\n",
"Ongoing Power Transition?",
((pwrdm54xx_in_transition(id) == 1) ? "YES" : "NO"));
}
fprintf(stream, "|---------------------------------------------------"
"-------------|\n\n");
return 0;
}
/* ------------------------------------------------------------------------*//**
* @FUNCTION powerdm_config_show
* @BRIEF decode and display power domain configuration
* @RETURNS 0 in case of success
* OMAPCONF_ERR_CPU
* OMAPCONF_ERR_ARG
* OMAPCONF_ERR_NOT_AVAILABLE
* @param[in,out] stream: output file
* @param[in] powerdm: power domain name
* @DESCRIPTION decode and display power domain configuration
*//*------------------------------------------------------------------------ */
int powerdm_config_show(FILE *stream, const char *powerdm)
{
int ret;
powerdm_info data;
pwrdm_state st_last, st_curr, st_tgt;
reg *pm_pwrstctrl;
reg *pm_pwrstst;
char s[64];
char s1[32], s2[32];
CHECK_NULL_ARG(stream, OMAPCONF_ERR_ARG);
CHECK_NULL_ARG(powerdm, OMAPCONF_ERR_ARG);
ret = _powerdm_info_get(powerdm, &data);
if (ret != 0) {
dprintf("%s(%s): could not retrieve powerdm_info struct!\n",
__func__, powerdm);
return OMAPCONF_ERR_NOT_AVAILABLE;
}
fprintf(stream,
"|----------------------------------------------------------------|\n");
strcpy(s, powerdm);
strcat(s, " Power Domain Configuration");
fprintf(stream, "| %-62s |\n", s);
fprintf(stream,
"|----------------------------------------------------------------|\n");
fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n", "Power State",
"Current", "Target", "Last");
fprintf(stream,
"|----------------------------------|---------|---------|---------|\n");
st_last = powerdm_state_get(powerdm, PWRDM_STATE_PREVIOUS);
st_curr = powerdm_state_get(powerdm, PWRDM_STATE_CURRENT);
st_tgt = powerdm_state_get(powerdm, PWRDM_STATE_TARGET);
fprintf(stream, "| %-32s | %-7s | %-7s | %-7s |\n",
"Domain", pwrdm_state_name_get(st_curr),
pwrdm_state_name_get(st_tgt), pwrdm_state_name_get(st_last));
if ((!powerdm_has_logic_ret_state_ctrl_bit(powerdm)) &&
(data.pwrstst == NULL))
goto powerdm_config_show_mem;
st_tgt = powerdm_target_logic_ret_state_get(powerdm);
if (st_tgt != PWRDM_STATE_MAX)
strcpy(s1, pwrdm_state_name_get(st_tgt));
else
strcpy(s1, "");
st_curr = powerdm_logic_state_get(powerdm);
if (st_curr != PWRDM_STATE_MAX)
strcpy(s2, pwrdm_state_name_get(st_curr));
else
strcpy(s2, "");
fprintf(stream, "| %-32s | %-7s | %-7s | |\n", "Logic", s2, s1);
powerdm_config_show_mem:
if (cpu_is_omap44xx()) {
pm_pwrstctrl = powerdm_pwrstctrl_reg_get(powerdm);
pm_pwrstst = powerdm_pwrstst_reg_get(powerdm);
ret = pwrdm44xx_config_show(stream, powerdm,
reg_addr_get(pm_pwrstctrl),
reg_read(pm_pwrstctrl),
reg_addr_get(pm_pwrstst),
reg_read(pm_pwrstst));
} else if (cpu_is_omap54xx()) {
ret = pwrdm54xx_config_show(stream, data);
} else {
fprintf(stderr,
"omapconf: %s(): cpu not supported!!!\n", __func__);
ret = OMAPCONF_ERR_CPU;
}
if (data.pwrstst != NULL) {
fprintf(stream,
"|----------------------------------------------------------------|\n");
fprintf(stream, "| %-32s | %-27s |\n",
"Ongoing Power Transition?",
((powerdm_in_transition(powerdm) == 1) ? "YES" : "NO"));
}
fprintf(stream,
"|----------------------------------------------------------------|\n\n");
return ret;
}
