static void imx_gpio_realize(DeviceState *dev, Error **errp)
{
IMXGPIOState *s = IMX_GPIO(dev);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpio_ops, s,
TYPE_IMX_GPIO, IMX_GPIO_MEM_SIZE);
qdev_init_gpio_in(DEVICE(s), imx_gpio_set, IMX_GPIO_PIN_COUNT);
qdev_init_gpio_out(DEVICE(s), s->output, IMX_GPIO_PIN_COUNT);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[0]);
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[1]);
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
}
static int pl181_init(SysBusDevice *dev)
{
pl181_state *s = FROM_SYSBUS(pl181_state, dev);
DriveInfo *dinfo;
memory_region_init_io(&s->iomem, &pl181_ops, s, "pl181", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq[0]);
sysbus_init_irq(dev, &s->irq[1]);
qdev_init_gpio_out(&s->busdev.qdev, s->cardstatus, 2);
dinfo = drive_get_next(IF_SD);
s->card = sd_init(dinfo ? dinfo->bdrv : NULL, 0);
return 0;
}
static int sparc32_dma_init1(SysBusDevice *dev)
{
DMAState *s = FROM_SYSBUS(DMAState, dev);
int dma_io_memory;
sysbus_init_irq(dev, &s->irq);
dma_io_memory = cpu_register_io_memory(dma_mem_read, dma_mem_write, s);
sysbus_init_mmio(dev, DMA_SIZE, dma_io_memory);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
qdev_init_gpio_out(&dev->qdev, &s->dev_reset, 1);
return 0;
}
static int sparc32_dma_init1(SysBusDevice *dev)
{
DMAState *s = FROM_SYSBUS(DMAState, dev);
int reg_size;
sysbus_init_irq(dev, &s->irq);
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, &dma_mem_ops, s, "dma", reg_size);
sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, dma_set_irq, 1);
qdev_init_gpio_out(&dev->qdev, s->gpio, 2);
return 0;
}
static int sp805_init(SysBusDevice *dev, const unsigned char *id)
{
int iomemtype;
sp805_state *s = FROM_SYSBUS(sp805_state, dev);
s->id = id;
iomemtype = cpu_register_io_memory(sp805_readfn,
sp805_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, iomemtype);
sysbus_init_irq(dev, &s->irq);
qdev_init_gpio_in(&dev->qdev, sp805_set_irq, 8);
qdev_init_gpio_out(&dev->qdev, s->out, 8);
sp805_reset(s);
register_savevm(&dev->qdev, "sp805_watchdog", -1, 1, sp805_save, sp805_load, s);
return 0;
}
static void xlx_iom_realize(DeviceState *dev, Error **errp)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(dev);
unsigned int i;
s->prefix = object_get_canonical_path(OBJECT(dev));
for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
RegisterInfo *r = &s->regs_info[i];
*r = (RegisterInfo) {
.data = (uint8_t *)&s->regs[i],
.data_size = sizeof(uint32_t),
.access = &pit_regs_info[i],
.debug = XILINX_IO_MODULE_PIT_ERR_DEBUG,
.prefix = s->prefix,
.opaque = s,
};
memory_region_init_io(&r->mem, OBJECT(dev), &iom_pit_ops, r,
r->access->name, 4);
memory_region_add_subregion(&s->iomem, i * 4, &r->mem);
}
if (s->cfg.use) {
s->bh = qemu_bh_new(pit_timer_hit, s);
s->ptimer = ptimer_init(s->bh);
ptimer_set_freq(s->ptimer, s->frequency);
/* IRQ out to pulse when present timer expires/reloads */
qdev_init_gpio_out(dev, &s->hit_out, 1);
/* IRQ in to enable pre-scalar mode. Routed from gpo1 */
qdev_init_gpio_in_named(dev, iom_pit_ps_config, "ps_config", 1);
/* hit_out of neighbouring PIT is received as hit_in */
qdev_init_gpio_in_named(dev, iom_pit_ps_hit_in, "ps_hit_in", 1);
}
}
static void xlx_iom_pit_init(Object *obj)
{
XilinxPIT *s = XILINX_IO_MODULE_PIT(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
memory_region_init_io(&s->iomem, obj, &iom_pit_ops, s,
TYPE_XILINX_IO_MODULE_PIT,
R_MAX * 4);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_irq(sbd, &s->irq);
}
static void macio_newworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
int i;
qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs));
object_property_add_link(obj, "pic", TYPE_OPENPIC,
(Object **) &ns->pic,
qdev_prop_allow_set_link_before_realize,
0, NULL);
for (i = 0; i < 2; i++) {
macio_init_ide(s, &ns->ide[i], sizeof(ns->ide[i]), i);
}
}
static void macio_oldworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
DeviceState *dev;
qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
object_initialize(&os->nvram, TYPE_MACIO_NVRAM);
dev = DEVICE(&os->nvram);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 4);
object_initialize(&os->ide, TYPE_MACIO_IDE);
qdev_set_parent_bus(DEVICE(&os->ide), sysbus_get_default());
memory_region_add_subregion(&s->bar, 0x1f000 + (1 * 0x1000), &os->ide.mem);
object_property_add_child(obj, "ide", OBJECT(&os->ide), NULL);
}
static int sparc32_dma_init1(SysBusDevice *sbd)
{
DeviceState *dev = DEVICE(sbd);
DMAState *s = SPARC32_DMA(dev);
int reg_size;
sysbus_init_irq(sbd, &s->irq);
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"dma", reg_size);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(dev, dma_set_irq, 1);
qdev_init_gpio_out(dev, s->gpio, 2);
return 0;
}
static void macio_oldworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
DeviceState *dev;
int i;
qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
dev = DEVICE(&os->nvram);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 4);
for (i = 0; i < 2; i++) {
macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i);
}
}
static int at91_pio_init(SysBusDevice *dev)
{
PIOState *s = FROM_SYSBUS(typeof (*s), dev);
int pio_regs;
sysbus_init_irq(dev, &s->parent_irq);
qdev_init_gpio_in(&dev->qdev, at91_pio_set_pin, PIO_PINS * 3);
qdev_init_gpio_out(&dev->qdev, s->out, PIO_PINS * 3);
pio_regs = cpu_register_io_memory(at91_pio_readfn, at91_pio_writefn, s, DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, PIO_SIZE, pio_regs);
at91_pio_reset(s);
qemu_register_reset(at91_pio_reset, s);
//register_savevm(&dev->qdev, "at91_pio", -1, 1, at91_pio_save, at91_pio_load, s);
vmstate_register(&dev->qdev, -1, &vmstate_at91sam9_pio, s);
return 0;
}
static void macio_newworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
int i;
gchar *name;
qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs));
for (i = 0; i < 2; i++) {
object_initialize(&ns->ide[i], TYPE_MACIO_IDE);
qdev_set_parent_bus(DEVICE(&ns->ide[i]), sysbus_get_default());
memory_region_add_subregion(&s->bar, 0x1f000 + ((i + 1) * 0x1000),
&ns->ide[i].mem);
name = g_strdup_printf("ide[%i]", i);
object_property_add_child(obj, name, OBJECT(&ns->ide[i]), NULL);
g_free(name);
}
}
static int stm32_button_init(SysBusDevice *dev, const char* id) {
stm32_button_state *s = FROM_SYSBUS(stm32_button_state, dev);
//Initialisation de la pin de sortie
//Initialisation of the output pin
qdev_init_gpio_out(&dev->qdev, &s->gpio_out, 1);
//Initialisation du Chardev
s->chr = qdev_init_chardev(&dev->qdev);
s->chr = qemu_chr_find(id);
if (s->chr) {
qemu_chr_add_handlers(s->chr, stm32_can_receive, stm32_receive, stm32_event, s);
}
stm32_button_reset(s);
vmstate_register(&dev->qdev, -1, &vmstate_stm32_button, s);
return 0;
}
static int max111x_init(SSISlave *dev, int inputs)
{
MAX111xState *s = FROM_SSI_SLAVE(MAX111xState, dev);
qdev_init_gpio_out(&dev->qdev, &s->interrupt, 1);
s->inputs = inputs;
/* TODO: add a user interface for setting these */
s->input[0] = 0xf0;
s->input[1] = 0xe0;
s->input[2] = 0xd0;
s->input[3] = 0xc0;
s->input[4] = 0xb0;
s->input[5] = 0xa0;
s->input[6] = 0x90;
s->input[7] = 0x80;
s->com = 0;
vmstate_register(&dev->qdev, -1, &vmstate_max111x, s);
return 0;
}
static void arm_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
ARMCPU *cpu = ARM_CPU(obj);
static bool inited;
cs->env_ptr = &cpu->env;
cpu_exec_init(&cpu->env);
cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
g_free, g_free);
#ifndef CONFIG_USER_ONLY
/* Our inbound IRQ and FIQ lines */
if (kvm_enabled()) {
qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 2);
} else {
qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 2);
}
cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_ptimer_cb, cpu);
cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
arm_gt_vtimer_cb, cpu);
qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
ARRAY_SIZE(cpu->gt_timer_outputs));
#endif
/* DTB consumers generally don't in fact care what the 'compatible'
* string is, so always provide some string and trust that a hypothetical
* picky DTB consumer will also provide a helpful error message.
*/
cpu->dtb_compatible = "qemu,unknown";
cpu->psci_version = 1; /* By default assume PSCI v0.1 */
cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
if (tcg_enabled() && !inited) {
inited = true;
arm_translate_init();
}
}
static int max111x_init(SSISlave *d, int inputs)
{
DeviceState *dev = DEVICE(d);
MAX111xState *s = MAX_111X(dev);
qdev_init_gpio_out(dev, &s->interrupt, 1);
s->inputs = inputs;
/* TODO: add a user interface for setting these */
s->input[0] = 0xf0;
s->input[1] = 0xe0;
s->input[2] = 0xd0;
s->input[3] = 0xc0;
s->input[4] = 0xb0;
s->input[5] = 0xa0;
s->input[6] = 0x90;
s->input[7] = 0x80;
s->com = 0;
vmstate_register(dev, -1, &vmstate_max111x, s);
return 0;
}
static void macio_oldworld_init(Object *obj)
{
MacIOState *s = MACIO(obj);
OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
DeviceState *dev;
int i;
qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
object_property_add_link(obj, "pic", TYPE_HEATHROW,
(Object **) &os->pic,
qdev_prop_allow_set_link_before_realize,
0, NULL);
object_initialize(&os->nvram, sizeof(os->nvram), TYPE_MACIO_NVRAM);
dev = DEVICE(&os->nvram);
qdev_prop_set_uint32(dev, "size", 0x2000);
qdev_prop_set_uint32(dev, "it_shift", 4);
for (i = 0; i < 2; i++) {
macio_init_ide(s, &os->ide[i], sizeof(os->ide[i]), i);
}
}
static void or_irq_init(Object *obj)
{
qemu_or_irq *s = OR_IRQ(obj);
qdev_init_gpio_out(DEVICE(obj), &s->out_irq, 1);
}
