static int reset_q6_trusted(void) { #if defined (CONFIG_SEC_DEBUG) int rc; // int ret,rc; // ret = local_src_enable(PLL_4); // if (ret) // return ret; printk(KERN_INFO "%s: enter\n", __func__); make_q6_proxy_votes(); pr_info("%s: PMIC 8901 S3 voltage=%d\n", __func__, pm8901_smps3_get_voltage()); rc = auth_and_reset_trusted(PAS_Q6); pr_info("%s: PMIC 8901 S3 voltage=%d\n", __func__, pm8901_smps3_get_voltage()); qdsp_clock_register_read(); dump_qdss_reg(); dump_counter_reg(); printk(KERN_INFO "%s: exit\n", __func__); return rc; #else printk(KERN_INFO "%s: enter\n", __func__); make_q6_proxy_votes(); printk(KERN_INFO "%s: exit\n", __func__); return auth_and_reset_trusted(PAS_Q6); #endif }
static int reset_q6_trusted(void) { #if defined (CONFIG_USA_MODEL_SGH_I727) int rc; printk(KERN_INFO "%s: enter\n", __func__); make_q6_proxy_votes(); pr_info("%s: PMIC 8901 S3 voltage=%d\n", __func__, pm8901_smps3_get_voltage()); rc = auth_and_reset_trusted(PAS_Q6); pr_info("%s: PMIC 8901 S3 voltage=%d\n", __func__, pm8901_smps3_get_voltage()); qdsp_clock_register_read(); printk(KERN_INFO "%s: exit\n", __func__); return rc; #else printk(KERN_INFO "%s: enter\n", __func__); make_q6_proxy_votes(); printk(KERN_INFO "%s: exit\n", __func__); return auth_and_reset_trusted(PAS_Q6); #endif }
static int reset_q6_untrusted(void) { #if defined (CONFIG_USA_MODEL_SGH_I727) u32 reg; int ret; ret = local_src_enable(PLL_4); if (ret) return ret; printk(KERN_INFO "%s: enter\n", __func__); make_q6_proxy_votes(); /*get the S3B voltage*/ pr_info("%s: PMIC 8901 S3 voltage=%d\n", __func__, pm8901_smps3_get_voltage()); /* Put Q6 into reset */ reg = readl(LCC_Q6_FUNC); reg |= Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | STOP_CORE | CORE_ARES; reg &= ~CORE_GFM4_CLK_EN; writel(reg, LCC_Q6_FUNC); /* Wait 8 AHB cycles for Q6 to be fully reset (AHB = 1.5Mhz) */ usleep_range(20, 30); /* Turn on Q6 memory */ reg |= CORE_GFM4_CLK_EN | CORE_L1_MEM_CORE_EN | CORE_TCM_MEM_CORE_EN | CORE_TCM_MEM_PERPH_EN; writel(reg, LCC_Q6_FUNC); /* Turn on Q6 core clocks and take core out of reset */ reg &= ~(CLAMP_IO | Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | CORE_ARES); writel(reg, LCC_Q6_FUNC); /* Wait for clocks to be enabled */ mb(); /* Program boot address */ writel((q6_start >> 12) & 0xFFFFF, QDSP6SS_RST_EVB); writel(Q6_STRAP_TCM_CONFIG | Q6_STRAP_TCM_BASE, QDSP6SS_STRAP_TCM); writel(Q6_STRAP_AHB_UPPER | Q6_STRAP_AHB_LOWER, QDSP6SS_STRAP_AHB); /* Wait for addresses to be programmed before starting Q6 */ mb(); /* Start Q6 instruction execution */ reg &= ~STOP_CORE; writel(reg, LCC_Q6_FUNC); pr_info("%s: PMIC 8901 S3 voltage=%d\n", __func__, pm8901_smps3_get_voltage()); qdsp_clock_register_read(); printk(KERN_INFO "%s: exit\n", __func__); return 0; #else u32 reg; printk(KERN_INFO "%s: enter\n", __func__); make_q6_proxy_votes(); /* Put Q6 into reset */ reg = readl(LCC_Q6_FUNC); reg |= Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | STOP_CORE | CORE_ARES; reg &= ~CORE_GFM4_CLK_EN; writel(reg, LCC_Q6_FUNC); /* Wait 8 AHB cycles for Q6 to be fully reset (AHB = 1.5Mhz) */ usleep_range(20, 30); /* Turn on Q6 memory */ reg |= CORE_GFM4_CLK_EN | CORE_L1_MEM_CORE_EN | CORE_TCM_MEM_CORE_EN | CORE_TCM_MEM_PERPH_EN; writel(reg, LCC_Q6_FUNC); /* Turn on Q6 core clocks and take core out of reset */ reg &= ~(CLAMP_IO | Q6SS_SS_ARES | Q6SS_ISDB_ARES | Q6SS_ETM_ARES | CORE_ARES); writel(reg, LCC_Q6_FUNC); /* Wait for clocks to be enabled */ mb(); /* Program boot address */ writel((q6_start >> 12) & 0xFFFFF, QDSP6SS_RST_EVB); writel(Q6_STRAP_TCM_CONFIG | Q6_STRAP_TCM_BASE, QDSP6SS_STRAP_TCM); writel(Q6_STRAP_AHB_UPPER | Q6_STRAP_AHB_LOWER, QDSP6SS_STRAP_AHB); /* Wait for addresses to be programmed before starting Q6 */ mb(); /* Start Q6 instruction execution */ reg &= ~STOP_CORE; writel(reg, LCC_Q6_FUNC); printk(KERN_INFO "%s: exit\n", __func__); return 0; #endif }
struct apr_svc_ch_dev *apr_tal_open(uint32_t svc, uint32_t dest, uint32_t dl, apr_svc_cb_fn func, void *priv) { int rc; if ((svc >= APR_CLIENT_MAX) || (dest >= APR_DEST_MAX) || (dl >= APR_DL_MAX)) { pr_err("apr_tal: Invalid params\n"); return NULL; } if (apr_svc_ch[dl][dest][svc].ch) { pr_err("apr_tal: This channel alreday openend\n"); return NULL; } mutex_lock(&apr_svc_ch[dl][dest][svc].m_lock); if (!apr_svc_ch[dl][dest][svc].dest_state) { rc = wait_event_timeout(apr_svc_ch[dl][dest][svc].dest, apr_svc_ch[dl][dest][svc].dest_state, msecs_to_jiffies(APR_OPEN_TIMEOUT_MS)); if (rc == 0) { pr_err("apr_tal:open timeout\n"); //pr_err("something wrong with lpass.. now restarting lpass\n"); mutex_unlock(&apr_svc_ch[dl][dest][svc].m_lock); qdsp_clock_register_read(); //panic("LPASS Crash"); return NULL; } pr_debug("apr_tal:Wakeup done\n"); apr_svc_ch[dl][dest][svc].dest_state = 0; } rc = smd_named_open_on_edge(svc_names[dest][svc], dest, &apr_svc_ch[dl][dest][svc].ch, &apr_svc_ch[dl][dest][svc], apr_tal_notify); if (rc < 0) { pr_err("apr_tal: smd_open failed %s\n", svc_names[dest][svc]); mutex_unlock(&apr_svc_ch[dl][dest][svc].m_lock); return NULL; } rc = wait_event_timeout(apr_svc_ch[dl][dest][svc].wait, (apr_svc_ch[dl][dest][svc].smd_state == 1), 5 * HZ); if (rc == 0) { pr_err("apr_tal:TIMEOUT for OPEN event\n"); mutex_unlock(&apr_svc_ch[dl][dest][svc].m_lock); return NULL; } if (!apr_svc_ch[dl][dest][svc].dest_state) { apr_svc_ch[dl][dest][svc].dest_state = 1; pr_debug("apr_tal:Waiting for apr svc init\n"); msleep(200); pr_debug("apr_tal:apr svc init done\n"); } apr_svc_ch[dl][dest][svc].smd_state = 0; apr_svc_ch[dl][dest][svc].func = func; apr_svc_ch[dl][dest][svc].priv = priv; mutex_unlock(&apr_svc_ch[dl][dest][svc].m_lock); return &apr_svc_ch[dl][dest][svc]; }