void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
MIPSnetState *s;
qemu_check_nic_model(nd, "mipsnet");
s = qemu_mallocz(sizeof(MIPSnetState));
register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
s->io_base = base;
s->irq = irq;
if (nd) {
memcpy(s->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
s->conf.vlan = nd->vlan;
s->conf.peer = nd->netdev;
s->nic = qemu_new_nic(&net_mipsnet_info, &s->conf,
nd->model, nd->name, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
}
mipsnet_reset(s);
vmstate_register(NULL, 0, &vmstate_mipsnet, s);
}
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
qemu_check_nic_model(nd, "dp83932");
s = qemu_mallocz(sizeof(dp8393xState));
s->mem_opaque = mem_opaque;
s->memory_rw = memory_rw;
s->it_shift = it_shift;
s->irq = irq;
s->watchdog = qemu_new_timer(vm_clock, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
s->conf.macaddr = nd->macaddr;
s->conf.vlan = nd->vlan;
s->conf.peer = nd->netdev;
s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s);
qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
qemu_register_reset(nic_reset, s);
nic_reset(s);
s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s);
cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index);
}
void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
MemoryRegion *address_space,
qemu_irq irq, void* mem_opaque,
void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write))
{
dp8393xState *s;
qemu_check_nic_model(nd, "dp83932");
s = g_malloc0(sizeof(dp8393xState));
s->address_space = address_space;
s->mem_opaque = mem_opaque;
s->memory_rw = memory_rw;
s->it_shift = it_shift;
s->irq = irq;
s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s);
s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */
s->conf.macaddr = nd->macaddr;
s->conf.peers.ncs[0] = nd->netdev;
s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s);
qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
qemu_register_reset(nic_reset, s);
nic_reset(s);
memory_region_init_io(&s->mmio, NULL, &dp8393x_ops, s,
"dp8393x", 0x40 << it_shift);
memory_region_add_subregion(address_space, base, &s->mmio);
}
void mipsnet_init (int base, qemu_irq irq, NICInfo *nd)
{
MIPSnetState *s;
qemu_check_nic_model(nd, "mipsnet");
s = qemu_mallocz(sizeof(MIPSnetState));
register_ioport_write(base, 36, 1, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 1, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 2, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 2, mipsnet_ioport_read, s);
register_ioport_write(base, 36, 4, mipsnet_ioport_write, s);
register_ioport_read(base, 36, 4, mipsnet_ioport_read, s);
s->io_base = base;
s->irq = irq;
if (nd && nd->vlan) {
s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
mipsnet_receive,
mipsnet_can_receive,
mipsnet_cleanup, s);
} else {
s->vc = NULL;
}
qemu_format_nic_info_str(s->vc, nd->macaddr);
mipsnet_reset(s);
register_savevm("mipsnet", 0, 0, mipsnet_save, mipsnet_load, s);
}
void *etraxfs_eth_init(NICInfo *nd, target_phys_addr_t base, int phyaddr)
{
struct etraxfs_dma_client *dma = NULL;
struct fs_eth *eth = NULL;
qemu_check_nic_model(nd, "fseth");
dma = qemu_mallocz(sizeof *dma * 2);
eth = qemu_mallocz(sizeof *eth);
dma[0].client.push = eth_tx_push;
dma[0].client.opaque = eth;
dma[1].client.opaque = eth;
dma[1].client.pull = NULL;
eth->dma_out = dma;
eth->dma_in = dma + 1;
/* Connect the phy. */
eth->phyaddr = phyaddr & 0x1f;
tdk_init(ð->phy);
mdio_attach(ð->mdio_bus, ð->phy, eth->phyaddr);
eth->ethregs = cpu_register_io_memory(eth_read, eth_write, eth);
cpu_register_physical_memory (base, 0x5c, eth->ethregs);
memcpy(eth->conf.macaddr.a, nd->macaddr, sizeof(nd->macaddr));
eth->conf.vlan = nd->vlan;
eth->conf.peer = nd->netdev;
eth->nic = qemu_new_nic(&net_etraxfs_info, ð->conf,
nd->model, nd->name, eth);
return dma;
}
static void overo_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
struct overo_s *s = (struct overo_s *) g_malloc0(sizeof(*s));
DriveInfo *dmtd = drive_get(IF_MTD, 0, 0);
DriveInfo *dsd = drive_get(IF_SD, 0, 0);
if (ram_size > 1024 * 1024 * 1024) {
fprintf(stderr, "overo: maximum permitted RAM size 1024MB\n");
exit(1);
}
if (!dmtd && !dsd) {
hw_error("%s: SD or NAND image required", __FUNCTION__);
}
s->cpu = omap3_mpu_init(omap3430, ram_size,
NULL, NULL, serial_hds[0], NULL);
s->nand = nand_init(dmtd ? dmtd->bdrv : NULL, NAND_MFR_MICRON, 0xba);
nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */
omap_gpmc_attach_nand(s->cpu->gpmc, OVERO_NAND_CS, s->nand);
if (dsd) {
omap3_mmc_attach(s->cpu->omap3_mmc[0], dsd->bdrv, 0, 0);
}
/* FAB revs >= 2516: 4030 interrupt is GPIO 0 (earlier ones were 112) */
s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c, 0),
qdev_get_gpio_in(s->cpu->gpio, 0),
NULL, NULL);
/* Wire up an I2C slave which returns EDID monitor information;
* newer Linux kernels won't turn on the display unless they
* detect a monitor over DDC.
*/
s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c, 2), "i2c-ddc", 0x50);
omap_lcd_panel_attach(s->cpu->dss);
/* Strictly this should be a LAN9221 */
if (nd_table[0].vlan) {
/* The ethernet chip hangs off the GPMC */
NICInfo *nd = &nd_table[0];
qemu_check_nic_model(nd, "lan9118");
s->eth = qdev_create(NULL, "lan9118");
qdev_set_nic_properties(s->eth, nd);
qdev_init_nofail(s->eth);
omap_gpmc_attach(s->cpu->gpmc, OVERO_NET_CS,
sysbus_mmio_get_region(sysbus_from_qdev(s->eth), 0));
sysbus_connect_irq(sysbus_from_qdev(s->eth), 0,
qdev_get_gpio_in(s->cpu->gpio, 176));
}
}
/* Legacy helper function. Should go away when machine config files are
implemented. */
void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
qemu_check_nic_model(nd, "smc91c111");
dev = qdev_create(NULL, "smc91c111");
qdev_set_nic_properties(dev, nd);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
/* Legacy helper function. Should go away when machine config files are
implemented. */
void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
qemu_check_nic_model(nd, "smc91c111");
dev = qdev_create(NULL, "smc91c111");
qdev_set_netdev(dev, nd);
qdev_init(dev);
s = sysbus_from_qdev(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
qemu_check_nic_model(nd, "cadence_gem");
dev = qdev_create(NULL, "cadence_gem");
qdev_set_nic_properties(dev, nd);
qdev_init_nofail(dev);
s = sysbus_from_qdev(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
static void lan9215_init(uint32_t base, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
/* This should be a 9215 but the 9118 is close enough */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "lan9118");
dev = qdev_create(NULL, "lan9118");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "mode_16bit", 1);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, base);
sysbus_connect_irq(s, 0, irq);
}
}
static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque,
const char *name, hwaddr size)
{
SysBusDevice *s;
NICInfo *nd = &nd_table[0];
/* In hardware this is a LAN9220; the LAN9118 is software compatible
* except that it doesn't support the checksum-offload feature.
*/
qemu_check_nic_model(nd, "lan9118");
mms->lan9118 = qdev_create(NULL, "lan9118");
qdev_set_nic_properties(mms->lan9118, nd);
qdev_init_nofail(mms->lan9118);
s = SYS_BUS_DEVICE(mms->lan9118);
sysbus_connect_irq(s, 0, get_sse_irq_in(mms, 16));
return sysbus_mmio_get_region(s, 0);
}
static void lance_init(NICInfo *nd, hwaddr leaddr,
void *dma_opaque, qemu_irq irq)
{
DeviceState *dev;
SysBusDevice *s;
qemu_irq reset;
qemu_check_nic_model(&nd_table[0], "lance");
dev = qdev_create(NULL, "lance");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_ptr(dev, "dma", dma_opaque);
qdev_init_nofail(dev);
s = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(s, 0, leaddr);
sysbus_connect_irq(s, 0, irq);
reset = qdev_get_gpio_in(dev, 0);
qdev_connect_gpio_out(dma_opaque, 0, reset);
}
void smc91c111_init(NICInfo *nd, uint32_t base, qemu_irq irq)
{
smc91c111_state *s;
int iomemtype;
qemu_check_nic_model(nd, "smc91c111");
s = (smc91c111_state *)qemu_mallocz(sizeof(smc91c111_state));
iomemtype = cpu_register_io_memory(0, smc91c111_readfn,
smc91c111_writefn, s);
cpu_register_physical_memory(base, 16, iomemtype);
s->irq = irq;
memcpy(s->macaddr, nd->macaddr, 6);
smc91c111_reset(s);
s->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name,
smc91c111_receive, smc91c111_can_receive, s);
qemu_format_nic_info_str(s->vc, s->macaddr);
/* ??? Save/restore. */
}
static void aw_a10_realize(DeviceState *dev, Error **errp)
{
AwA10State *s = AW_A10(dev);
SysBusDevice *sysbusdev;
uint8_t i;
qemu_irq fiq, irq;
Error *err = NULL;
object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
irq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ);
fiq = qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ);
object_property_set_bool(OBJECT(&s->intc), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
sysbusdev = SYS_BUS_DEVICE(&s->intc);
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIC_REG_BASE);
sysbus_connect_irq(sysbusdev, 0, irq);
sysbus_connect_irq(sysbusdev, 1, fiq);
for (i = 0; i < AW_A10_PIC_INT_NR; i++) {
s->irq[i] = qdev_get_gpio_in(DEVICE(&s->intc), i);
}
object_property_set_bool(OBJECT(&s->timer), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
sysbusdev = SYS_BUS_DEVICE(&s->timer);
sysbus_mmio_map(sysbusdev, 0, AW_A10_PIT_REG_BASE);
sysbus_connect_irq(sysbusdev, 0, s->irq[22]);
sysbus_connect_irq(sysbusdev, 1, s->irq[23]);
sysbus_connect_irq(sysbusdev, 2, s->irq[24]);
sysbus_connect_irq(sysbusdev, 3, s->irq[25]);
sysbus_connect_irq(sysbusdev, 4, s->irq[67]);
sysbus_connect_irq(sysbusdev, 5, s->irq[68]);
memory_region_init_ram(&s->sram_a, OBJECT(dev), "sram A", 48 * KiB,
&error_fatal);
memory_region_add_subregion(get_system_memory(), 0x00000000, &s->sram_a);
create_unimplemented_device("a10-sram-ctrl", 0x01c00000, 4 * KiB);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], TYPE_AW_EMAC);
qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
}
object_property_set_bool(OBJECT(&s->emac), true, "realized", &err);
if (err != NULL) {
error_propagate(errp, err);
return;
}
sysbusdev = SYS_BUS_DEVICE(&s->emac);
sysbus_mmio_map(sysbusdev, 0, AW_A10_EMAC_BASE);
sysbus_connect_irq(sysbusdev, 0, s->irq[55]);
object_property_set_bool(OBJECT(&s->sata), true, "realized", &err);
if (err) {
error_propagate(errp, err);
return;
}
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sata), 0, AW_A10_SATA_BASE);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sata), 0, s->irq[56]);
/* FIXME use a qdev chardev prop instead of serial_hd() */
serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, s->irq[1],
115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
}
static void mips_jazz_init(MachineState *machine,
enum jazz_model_e jazz_model)
{
MemoryRegion *address_space = get_system_memory();
char *filename;
int bios_size, n;
MIPSCPU *cpu;
CPUClass *cc;
CPUMIPSState *env;
qemu_irq *i8259;
rc4030_dma *dmas;
IOMMUMemoryRegion *rc4030_dma_mr;
MemoryRegion *isa_mem = g_new(MemoryRegion, 1);
MemoryRegion *isa_io = g_new(MemoryRegion, 1);
MemoryRegion *rtc = g_new(MemoryRegion, 1);
MemoryRegion *i8042 = g_new(MemoryRegion, 1);
MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
NICInfo *nd;
DeviceState *dev, *rc4030;
SysBusDevice *sysbus;
ISABus *isa_bus;
ISADevice *pit;
DriveInfo *fds[MAX_FD];
qemu_irq esp_reset, dma_enable;
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios2 = g_new(MemoryRegion, 1);
/* init CPUs */
cpu = MIPS_CPU(cpu_create(machine->cpu_type));
env = &cpu->env;
qemu_register_reset(main_cpu_reset, cpu);
/* Chipset returns 0 in invalid reads and do not raise data exceptions.
* However, we can't simply add a global memory region to catch
* everything, as memory core directly call unassigned_mem_read/write
* on some invalid accesses, which call do_unassigned_access on the
* CPU, which raise an exception.
* Handle that case by hijacking the do_unassigned_access method on
* the CPU, and do not raise exceptions for data access. */
cc = CPU_GET_CLASS(cpu);
real_do_unassigned_access = cc->do_unassigned_access;
cc->do_unassigned_access = mips_jazz_do_unassigned_access;
/* allocate RAM */
memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram",
machine->ram_size);
memory_region_add_subregion(address_space, 0, ram);
memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE,
&error_fatal);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios,
0, MAGNUM_BIOS_SIZE);
memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
/* load the BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image_targphys(filename, 0xfff00000LL,
MAGNUM_BIOS_SIZE);
g_free(filename);
} else {
bios_size = -1;
}
if ((bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) && !qtest_enabled()) {
error_report("Could not load MIPS bios '%s'", bios_name);
exit(1);
}
/* Init CPU internal devices */
cpu_mips_irq_init_cpu(cpu);
cpu_mips_clock_init(cpu);
/* Chipset */
rc4030 = rc4030_init(&dmas, &rc4030_dma_mr);
sysbus = SYS_BUS_DEVICE(rc4030);
sysbus_connect_irq(sysbus, 0, env->irq[6]);
sysbus_connect_irq(sysbus, 1, env->irq[3]);
memory_region_add_subregion(address_space, 0x80000000,
sysbus_mmio_get_region(sysbus, 0));
memory_region_add_subregion(address_space, 0xf0000000,
sysbus_mmio_get_region(sysbus, 1));
memory_region_init_io(dma_dummy, NULL, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
/* ISA bus: IO space at 0x90000000, mem space at 0x91000000 */
memory_region_init(isa_io, NULL, "isa-io", 0x00010000);
memory_region_init(isa_mem, NULL, "isa-mem", 0x01000000);
memory_region_add_subregion(address_space, 0x90000000, isa_io);
memory_region_add_subregion(address_space, 0x91000000, isa_mem);
isa_bus = isa_bus_new(NULL, isa_mem, isa_io, &error_abort);
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
DMA_init(isa_bus, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
/* Video card */
switch (jazz_model) {
case JAZZ_MAGNUM:
dev = qdev_create(NULL, "sysbus-g364");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x60080000);
sysbus_mmio_map(sysbus, 1, 0x40000000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 3));
{
/* Simple ROM, so user doesn't have to provide one */
MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000,
&error_fatal);
memory_region_set_readonly(rom_mr, true);
uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
memory_region_add_subregion(address_space, 0x60000000, rom_mr);
rom[0] = 0x10; /* Mips G364 */
}
break;
case JAZZ_PICA61:
isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
break;
default:
break;
}
/* Network controller */
for (n = 0; n < nb_nics; n++) {
nd = &nd_table[n];
if (!nd->model)
nd->model = g_strdup("dp83932");
if (strcmp(nd->model, "dp83932") == 0) {
qemu_check_nic_model(nd, "dp83932");
dev = qdev_create(NULL, "dp8393x");
qdev_set_nic_properties(dev, nd);
qdev_prop_set_uint8(dev, "it_shift", 2);
qdev_prop_set_ptr(dev, "dma_mr", rc4030_dma_mr);
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80001000);
sysbus_mmio_map(sysbus, 1, 0x8000b000);
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(rc4030, 4));
break;
} else if (is_help_option(nd->model)) {
fprintf(stderr, "qemu: Supported NICs: dp83932\n");
exit(1);
} else {
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
exit(1);
}
}
/* SCSI adapter */
esp_init(0x80002000, 0,
rc4030_dma_read, rc4030_dma_write, dmas[0],
qdev_get_gpio_in(rc4030, 5), &esp_reset, &dma_enable);
/* Floppy */
for (n = 0; n < MAX_FD; n++) {
fds[n] = drive_get(IF_FLOPPY, 0, n);
}
/* FIXME: we should enable DMA with a custom IsaDma device */
fdctrl_init_sysbus(qdev_get_gpio_in(rc4030, 1), -1, 0x80003000, fds);
/* Real time clock */
rtc_init(isa_bus, 1980, NULL);
memory_region_init_io(rtc, NULL, &rtc_ops, NULL, "rtc", 0x1000);
memory_region_add_subregion(address_space, 0x80004000, rtc);
/* Keyboard (i8042) */
i8042_mm_init(qdev_get_gpio_in(rc4030, 6), qdev_get_gpio_in(rc4030, 7),
i8042, 0x1000, 0x1);
memory_region_add_subregion(address_space, 0x80005000, i8042);
/* Serial ports */
if (serial_hds[0]) {
serial_mm_init(address_space, 0x80006000, 0,
qdev_get_gpio_in(rc4030, 8), 8000000/16,
serial_hds[0], DEVICE_NATIVE_ENDIAN);
}
if (serial_hds[1]) {
serial_mm_init(address_space, 0x80007000, 0,
qdev_get_gpio_in(rc4030, 9), 8000000/16,
serial_hds[1], DEVICE_NATIVE_ENDIAN);
}
/* Parallel port */
if (parallel_hds[0])
parallel_mm_init(address_space, 0x80008000, 0,
qdev_get_gpio_in(rc4030, 0), parallel_hds[0]);
/* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
/* NVRAM */
dev = qdev_create(NULL, "ds1225y");
qdev_init_nofail(dev);
sysbus = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(sysbus, 0, 0x80009000);
/* LED indicator */
sysbus_create_simple("jazz-led", 0x8000f000, NULL);
}
/* ram_size must be set to match the upper bound of memory in the
* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
* normally 0xff900000 or -m 4089. When running this board on a
* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
* device tree and pass -m 2047 to QEMU.
*/
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
DeviceState *dev = NULL;
SysBusDevice *busdev;
qemu_irq pic[128];
int n;
qemu_irq cpu_irq[4];
qemu_irq cpu_fiq[4];
MemoryRegion *sysram;
MemoryRegion *dram;
MemoryRegion *sysmem;
char *sysboot_filename;
switch (machine_id) {
case CALXEDA_HIGHBANK:
machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a9");
break;
case CALXEDA_MIDWAY:
machine->cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
break;
default:
assert(0);
}
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj;
ARMCPU *cpu;
cpuobj = object_new(machine->cpu_type);
cpu = ARM_CPU(cpuobj);
object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_SMC,
"psci-conduit", &error_abort);
if (n) {
/* Secondary CPUs start in PSCI powered-down state */
object_property_set_bool(cpuobj, true,
"start-powered-off", &error_abort);
}
if (object_property_find(cpuobj, "reset-cbar", NULL)) {
object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
"reset-cbar", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
}
sysmem = get_system_memory();
dram = g_new(MemoryRegion, 1);
memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, dram);
sysram = g_new(MemoryRegion, 1);
memory_region_init_ram_nomigrate(sysram, NULL, "highbank.sysram", 0x8000,
&error_fatal);
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
if (bios_name != NULL) {
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (sysboot_filename != NULL) {
if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
error_report("Unable to load %s", bios_name);
exit(1);
}
g_free(sysboot_filename);
} else {
error_report("Unable to find %s", bios_name);
exit(1);
}
}
switch (machine_id) {
case CALXEDA_HIGHBANK:
dev = qdev_create(NULL, "l2x0");
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xfff12000);
dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV);
break;
case CALXEDA_MIDWAY:
dev = qdev_create(NULL, TYPE_A15MPCORE_PRIV);
break;
}
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
sysbus_connect_irq(busdev, n + smp_cpus, cpu_fiq[n]);
}
for (n = 0; n < 128; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
dev = qdev_create(NULL, "sp804");
qdev_prop_set_uint32(dev, "freq0", 150000000);
qdev_prop_set_uint32(dev, "freq1", 150000000);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xfff34000);
sysbus_connect_irq(busdev, 0, pic[18]);
pl011_create(0xfff36000, pic[20], serial_hds[0]);
dev = qdev_create(NULL, TYPE_HIGHBANK_REGISTERS);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xfff3c000);
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
sysbus_create_simple("pl061", 0xfff31000, pic[15]);
sysbus_create_simple("pl061", 0xfff32000, pic[16]);
sysbus_create_simple("pl061", 0xfff33000, pic[17]);
sysbus_create_simple("pl031", 0xfff35000, pic[19]);
sysbus_create_simple("pl022", 0xfff39000, pic[23]);
sysbus_create_simple(TYPE_SYSBUS_AHCI, 0xffe08000, pic[83]);
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "xgmac");
dev = qdev_create(NULL, "xgmac");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
qemu_check_nic_model(&nd_table[1], "xgmac");
dev = qdev_create(NULL, "xgmac");
qdev_set_nic_properties(dev, &nd_table[1]);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
}
/* TODO create and connect IDE devices for ide_drive_get() */
highbank_binfo.ram_size = ram_size;
highbank_binfo.kernel_filename = kernel_filename;
highbank_binfo.kernel_cmdline = kernel_cmdline;
highbank_binfo.initrd_filename = initrd_filename;
/* highbank requires a dtb in order to boot, and the dtb will override
* the board ID. The following value is ignored, so set it to -1 to be
* clear that the value is meaningless.
*/
highbank_binfo.board_id = -1;
highbank_binfo.nb_cpus = smp_cpus;
highbank_binfo.loader_start = 0;
highbank_binfo.write_secondary_boot = hb_write_secondary;
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
if (!kvm_enabled()) {
highbank_binfo.board_setup_addr = BOARD_SETUP_ADDR;
highbank_binfo.write_board_setup = hb_write_board_setup;
highbank_binfo.secure_board_setup = true;
} else {
warn_report("cannot load built-in Monitor support "
"if KVM is enabled. Some guests (such as Linux) "
"may not boot.");
}
arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
}
static void reptar_init(MachineState *machine)
{
MemoryRegion *sysmem = get_system_memory();
struct reptar_s *s = (struct reptar_s *)g_malloc0(sizeof(*s));
DriveInfo *dmtd = NULL, *dsd = NULL, *pflash = NULL;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
/* (DRE) */
uint32_t pflash_size = 16 << 10; /* 16 KB */
if (ram_size > 1024 * 1024 * 1024) {
fprintf(stderr, "reptar: maximum permitted RAM size 1024MB\n");
exit(1);
}
/* Check if we are in -kernel u-boot.bin mode */
if (kernel_filename) {
/* (DRE) We do the following in order to retrieve the kernel filename during the boot process.
* For example, if qemu was launched with -kernel u-boot.bin */
reptar_binfo.ram_size = ram_size;
reptar_binfo.kernel_filename = kernel_filename;
reptar_binfo.kernel_cmdline = kernel_cmdline;
reptar_binfo.initrd_filename = initrd_filename;
reptar_binfo.loader_start = 0x40014100; /* Start of small bootloader*/
reptar_binfo.board_id = 0;
} else
reptar_binfo.kernel_filename = NULL;
s->cpu = omap3_mpu_init(sysmem, omap3430, ram_size, NULL, NULL, serial_hds[0], NULL);
pflash = drive_get(IF_PFLASH, 0, 0);
if (pflash) {
if (!pflash_cfi02_register(0x30000000,
NULL,
"reptar.nand_flash",
pflash_size,
blk_by_legacy_dinfo(pflash),
sector_len,
pflash_size / sector_len,
1, 2, 0, 0, 0, 0, 0x555, 0x2AA, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1);
}
}
else {
dmtd = drive_get(IF_MTD, 0, 0);
s->nand = nand_init(dmtd ? blk_by_legacy_dinfo(dmtd) : NULL, NAND_MFR_MICRON, 0xba);
nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */
omap_gpmc_attach_nand(s->cpu->gpmc, REPTAR_NAND_CS, s->nand);
}
/*
* (DRE) Define MMC if any
*/
dsd = drive_get(IF_SD, 0, 0);
if (dsd)
omap3_mmc_attach(s->cpu->omap3_mmc[0], blk_by_legacy_dinfo(dsd), 0, 0);
if (!pflash && !dmtd && !dsd)
hw_error("%s: SD or NAND image required", __FUNCTION__);
/* FAB revs >= 2516: 4030 interrupt is GPIO 0 (earlier ones were 112) */
s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c[0]),
qdev_get_gpio_in(s->cpu->gpio, 0),
NULL,
NULL);
/* Wire up an I2C slave which returns EDID monitor information;
* newer Linux kernels won't turn on the display unless they
* detect a monitor over DDC.
*/
s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c[2]), "i2c-ddc", 0x50);
omap_lcd_panel_attach(s->cpu->dss);
/* Strictly this should be a LAN9221 */
#if 0
if (nd_table[0].vlan) {
#endif /* 0 */
/* The ethernet chip hangs off the GPMC */
NICInfo *nd = &nd_table[0];
qemu_check_nic_model(nd, "lan9118");
s->eth = qdev_create(NULL, "lan9118");
qdev_set_nic_properties(s->eth, nd);
qdev_init_nofail(s->eth);
omap_gpmc_attach(s->cpu->gpmc, REPTAR_NET_CS,
sysbus_mmio_get_region(SYS_BUS_DEVICE(s->eth), 0));
sysbus_connect_irq(SYS_BUS_DEVICE(s->eth), 0, qdev_get_gpio_in(s->cpu->gpio, 29));
#if 0
}
#endif /* 0 */
// Create reptar_sp6 with it's base address
s->sp6 = sysbus_create_simple("reptar_sp6",0x18000000,NULL);
// Connect reptar_sp6 to GPIO10 for the IRQ
sysbus_connect_irq(SYS_BUS_DEVICE(s->sp6), 0, qdev_get_gpio_in(s->cpu->gpio, 10));
}
static void
petalogix_ml605_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
Object *ds, *cs;
MicroBlazeCPU *cpu;
SysBusDevice *busdev;
DriveInfo *dinfo;
int i;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
/* init CPUs */
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort);
/* Use FPU but don't use floating point conversion and square
* root instructions
*/
object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
&error_abort);
object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE, &error_fatal);
vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size,
&error_fatal);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
(64 * 1024), FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0);
dev = qdev_create(NULL, "xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
irq[UART16550_IRQ], 115200, serial_hds[0],
DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
/* axi ethernet and dma initialization. */
qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
dma = qdev_create(NULL, "xlnx.axi-dma");
/* FIXME: attach to the sysbus instead */
object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0),
NULL);
object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma),
NULL);
ds = object_property_get_link(OBJECT(dma),
"axistream-connected-target", NULL);
cs = object_property_get_link(OBJECT(dma),
"axistream-control-connected-target", NULL);
qdev_set_nic_properties(eth0, &nd_table[0]);
qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
qdev_prop_set_uint32(eth0, "txmem", 0x1000);
object_property_set_link(OBJECT(eth0), OBJECT(ds),
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(eth0), OBJECT(cs),
"axistream-control-connected", &error_abort);
qdev_init_nofail(eth0);
sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
ds = object_property_get_link(OBJECT(eth0),
"axistream-connected-target", NULL);
cs = object_property_get_link(OBJECT(eth0),
"axistream-control-connected-target", NULL);
qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000);
object_property_set_link(OBJECT(dma), OBJECT(ds),
"axistream-connected", &error_abort);
object_property_set_link(OBJECT(dma), OBJECT(cs),
"axistream-control-connected", &error_abort);
qdev_init_nofail(dma);
sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
{
SSIBus *spi;
dev = qdev_create(NULL, "xlnx.xps-spi");
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, SPI_BASEADDR);
sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]);
spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
for (i = 0; i < NUM_SPI_FLASHES; i++) {
qemu_irq cs_line;
dev = ssi_create_slave(spi, "n25q128");
cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0);
sysbus_connect_irq(busdev, i+1, cs_line);
}
}
/* setup PVR to match kernel settings */
cpu->env.pvr.regs[4] = 0xc56b8000;
cpu->env.pvr.regs[5] = 0xc56be000;
cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */
microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size,
machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
NULL);
}
static void
petalogix_s3adsp1800_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
DeviceState *dev;
MicroBlazeCPU *cpu;
DriveInfo *dinfo;
int i;
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory();
cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU));
object_property_set_str(OBJECT(cpu), "7.10.d", "version", &error_abort);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL,
"petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE,
&error_fatal);
memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram",
ram_size, &error_fatal);
memory_region_add_subregion(sysmem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
64 * KiB, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);
dev = qdev_create(NULL, "xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
xilinx_uartlite_create(UARTLITE_BASEADDR, irq[UARTLITE_IRQ],
serial_hd(0));
/* 2 timers at irq 2 @ 62 Mhz. */
dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
microblaze_load_kernel(cpu, ddr_base, ram_size,
machine->initrd_filename,
BINARY_DEVICE_TREE_FILE,
NULL);
}
static void
petalogix_s3adsp1800_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
const char *cpu_model = args->cpu_model;
DeviceState *dev;
MicroBlazeCPU *cpu;
DriveInfo *dinfo;
int i;
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32];
MemoryRegion *sysmem = get_system_memory();
/* init CPUs */
if (cpu_model == NULL) {
cpu_model = "microblaze";
}
cpu = cpu_mb_init(cpu_model);
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, NULL,
"petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram", ram_size);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(sysmem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);
printf("load of flash = %d to %08X\n",
load_image_targphys(args->initrd_filename, 0x87000000, FLASH_SIZE),
0x87000000);
dev = qdev_create(NULL, "xlnx.xps-intc");
qdev_prop_set_uint32(dev, "kind-of-intr",
1 << ETHLITE_IRQ | 1 << UARTLITE_IRQ);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ));
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
sysbus_create_simple("xlnx.xps-uartlite", UARTLITE_BASEADDR,
irq[UARTLITE_IRQ]);
/* 2 timers at irq 2 @ 62 Mhz. */
dev = qdev_create(NULL, "xlnx.xps-timer");
qdev_prop_set_uint32(dev, "one-timer-only", 0);
qdev_prop_set_uint32(dev, "clock-frequency", 62 * 1000000);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
qemu_check_nic_model(&nd_table[0], "xlnx.xps-ethernetlite");
dev = qdev_create(NULL, "xlnx.xps-ethernetlite");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
microblaze_load_kernel(cpu, ddr_base, ram_size,
args->initrd_filename,
BINARY_DEVICE_TREE_FILE,
machine_cpu_reset, NULL);
}
/* ram_size must be set to match the upper bound of memory in the
* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
* normally 0xff900000 or -m 4089. When running this board on a
* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
* device tree and pass -m 2047 to QEMU.
*/
static void highbank_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUARMState *env = NULL;
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq *irqp;
qemu_irq pic[128];
int n;
qemu_irq cpu_irq[4];
MemoryRegion *sysram;
MemoryRegion *dram;
MemoryRegion *sysmem;
char *sysboot_filename;
if (!cpu_model) {
cpu_model = "cortex-a9";
}
for (n = 0; n < smp_cpus; n++) {
ARMCPU *cpu;
cpu = cpu_arm_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
/* This will become a QOM property eventually */
cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
}
sysmem = get_system_memory();
dram = g_new(MemoryRegion, 1);
memory_region_init_ram(dram, "highbank.dram", ram_size);
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, dram);
sysram = g_new(MemoryRegion, 1);
memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
if (bios_name != NULL) {
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (sysboot_filename != NULL) {
uint32_t filesize = get_image_size(sysboot_filename);
if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
hw_error("Unable to load %s\n", bios_name);
}
} else {
hw_error("Unable to find %s\n", bios_name);
}
}
dev = qdev_create(NULL, "a9mpcore_priv");
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
}
for (n = 0; n < 128; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
dev = qdev_create(NULL, "l2x0");
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, 0xfff12000);
dev = qdev_create(NULL, "sp804");
qdev_prop_set_uint32(dev, "freq0", 150000000);
qdev_prop_set_uint32(dev, "freq1", 150000000);
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, 0xfff34000);
sysbus_connect_irq(busdev, 0, pic[18]);
sysbus_create_simple("pl011", 0xfff36000, pic[20]);
dev = qdev_create(NULL, "highbank-regs");
qdev_init_nofail(dev);
busdev = sysbus_from_qdev(dev);
sysbus_mmio_map(busdev, 0, 0xfff3c000);
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
sysbus_create_simple("pl061", 0xfff31000, pic[15]);
sysbus_create_simple("pl061", 0xfff32000, pic[16]);
sysbus_create_simple("pl061", 0xfff33000, pic[17]);
sysbus_create_simple("pl031", 0xfff35000, pic[19]);
sysbus_create_simple("pl022", 0xfff39000, pic[23]);
sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
if (nd_table[0].vlan) {
qemu_check_nic_model(&nd_table[0], "xgmac");
dev = qdev_create(NULL, "xgmac");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);
qemu_check_nic_model(&nd_table[1], "xgmac");
dev = qdev_create(NULL, "xgmac");
qdev_set_nic_properties(dev, &nd_table[1]);
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
}
highbank_binfo.ram_size = ram_size;
highbank_binfo.kernel_filename = kernel_filename;
highbank_binfo.kernel_cmdline = kernel_cmdline;
highbank_binfo.initrd_filename = initrd_filename;
/* highbank requires a dtb in order to boot, and the dtb will override
* the board ID. The following value is ignored, so set it to -1 to be
* clear that the value is meaningless.
*/
highbank_binfo.board_id = -1;
highbank_binfo.nb_cpus = smp_cpus;
highbank_binfo.loader_start = 0;
highbank_binfo.write_secondary_boot = hb_write_secondary;
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
arm_load_kernel(first_cpu, &highbank_binfo);
}
/* ram_size must be set to match the upper bound of memory in the
* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
* normally 0xff900000 or -m 4089. When running this board on a
* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
* device tree and pass -m 2047 to QEMU.
*/
static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
{
ram_addr_t ram_size = machine->ram_size;
const char *cpu_model = machine->cpu_model;
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
const char *initrd_filename = machine->initrd_filename;
DeviceState *dev = NULL;
SysBusDevice *busdev;
qemu_irq pic[128];
int n;
qemu_irq cpu_irq[4];
MemoryRegion *sysram;
MemoryRegion *dram;
MemoryRegion *sysmem;
char *sysboot_filename;
if (!cpu_model) {
switch (machine_id) {
case CALXEDA_HIGHBANK:
cpu_model = "cortex-a9";
break;
case CALXEDA_MIDWAY:
cpu_model = "cortex-a15";
break;
}
}
for (n = 0; n < smp_cpus; n++) {
ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
Object *cpuobj;
ARMCPU *cpu;
Error *err = NULL;
if (!oc) {
error_report("Unable to find CPU definition");
exit(1);
}
cpuobj = object_new(object_class_get_name(oc));
cpu = ARM_CPU(cpuobj);
/* By default A9 and A15 CPUs have EL3 enabled. This board does not
* currently support EL3 so the CPU EL3 property is disabled before
* realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
object_property_set_bool(cpuobj, false, "has_el3", &err);
if (err) {
error_report_err(err);
exit(1);
}
}
if (object_property_find(cpuobj, "reset-cbar", NULL)) {
object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
"reset-cbar", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
}
sysmem = get_system_memory();
dram = g_new(MemoryRegion, 1);
memory_region_allocate_system_memory(dram, NULL, "highbank.dram", ram_size);
/* SDRAM at address zero. */
memory_region_add_subregion(sysmem, 0, dram);
sysram = g_new(MemoryRegion, 1);
memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000,
&error_abort);
memory_region_add_subregion(sysmem, 0xfff88000, sysram);
if (bios_name != NULL) {
sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (sysboot_filename != NULL) {
if (load_image_targphys(sysboot_filename, 0xfff88000, 0x8000) < 0) {
hw_error("Unable to load %s\n", bios_name);
}
g_free(sysboot_filename);
} else {
hw_error("Unable to find %s\n", bios_name);
}
}
switch (machine_id) {
case CALXEDA_HIGHBANK:
dev = qdev_create(NULL, "l2x0");
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xfff12000);
dev = qdev_create(NULL, "a9mpcore_priv");
break;
case CALXEDA_MIDWAY:
dev = qdev_create(NULL, "a15mpcore_priv");
break;
}
qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
for (n = 0; n < smp_cpus; n++) {
sysbus_connect_irq(busdev, n, cpu_irq[n]);
}
for (n = 0; n < 128; n++) {
pic[n] = qdev_get_gpio_in(dev, n);
}
dev = qdev_create(NULL, "sp804");
qdev_prop_set_uint32(dev, "freq0", 150000000);
qdev_prop_set_uint32(dev, "freq1", 150000000);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xfff34000);
sysbus_connect_irq(busdev, 0, pic[18]);
sysbus_create_simple("pl011", 0xfff36000, pic[20]);
dev = qdev_create(NULL, "highbank-regs");
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0xfff3c000);
sysbus_create_simple("pl061", 0xfff30000, pic[14]);
sysbus_create_simple("pl061", 0xfff31000, pic[15]);
sysbus_create_simple("pl061", 0xfff32000, pic[16]);
sysbus_create_simple("pl061", 0xfff33000, pic[17]);
sysbus_create_simple("pl031", 0xfff35000, pic[19]);
sysbus_create_simple("pl022", 0xfff39000, pic[23]);
sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
if (nd_table[0].used) {
qemu_check_nic_model(&nd_table[0], "xgmac");
dev = qdev_create(NULL, "xgmac");
qdev_set_nic_properties(dev, &nd_table[0]);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
qemu_check_nic_model(&nd_table[1], "xgmac");
dev = qdev_create(NULL, "xgmac");
qdev_set_nic_properties(dev, &nd_table[1]);
qdev_init_nofail(dev);
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
}
highbank_binfo.ram_size = ram_size;
highbank_binfo.kernel_filename = kernel_filename;
highbank_binfo.kernel_cmdline = kernel_cmdline;
highbank_binfo.initrd_filename = initrd_filename;
/* highbank requires a dtb in order to boot, and the dtb will override
* the board ID. The following value is ignored, so set it to -1 to be
* clear that the value is meaningless.
*/
highbank_binfo.board_id = -1;
highbank_binfo.nb_cpus = smp_cpus;
highbank_binfo.loader_start = 0;
highbank_binfo.write_secondary_boot = hb_write_secondary;
highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
}
void xbox_init_common(MachineState *machine,
const uint8_t *eeprom,
PCIBus **pci_bus_out,
ISABus **isa_bus_out)
{
PCMachineState *pcms = PC_MACHINE(machine);
// PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
MemoryRegion *system_memory = get_system_memory();
// MemoryRegion *system_io = get_system_io();
int i;
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq *i8259;
// qemu_irq smi_irq; // XBOX_TODO: SMM support?
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
// ISADevice *pit;
MemoryRegion *ram_memory;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
I2CBus *smbus;
PCIBus *agp_bus;
pc_cpus_init(pcms);
pci_memory = g_new(MemoryRegion, 1);
memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
rom_memory = pci_memory;
// pc_guest_info_init(pcms);
/* allocate ram and load rom/bios */
xbox_memory_init(pcms, system_memory, rom_memory, &ram_memory);
gsi_state = g_malloc0(sizeof(*gsi_state));
pcms->gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
xbox_pci_init(pcms->gsi,
get_system_memory(), get_system_io(),
pci_memory, ram_memory,
&pci_bus,
&isa_bus,
&smbus,
&agp_bus);
pcms->bus = pci_bus;
isa_bus_irqs(isa_bus, pcms->gsi);
i8259 = i8259_init(isa_bus, pc_allocate_cpu_irq());
for (i = 0; i < ISA_NUM_IRQS; i++) {
gsi_state->i8259_irq[i] = i8259[i];
}
g_free(i8259);
pc_register_ferr_irq(pcms->gsi[13]);
/* init basic PC hardware */
pcms->pit = 1; // XBOX_FIXME: What's the right way to do this?
rtc_state = mc146818_rtc_init(isa_bus, 2000, NULL);
// qemu_register_boot_set(pc_boot_set, rtc_state);
ISADevice *pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
ide_drive_get(hd, ARRAY_SIZE(hd));
PCIDevice *ide_dev = pci_piix3_ide_init(pci_bus, hd, PCI_DEVFN(9, 0));
idebus[0] = qdev_get_child_bus(&ide_dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&ide_dev->qdev, "ide.1");
// xbox bios wants this bit pattern set to mark the data as valid
uint8_t bits = 0x55;
for (i = 0x10; i < 0x70; i++) {
rtc_set_memory(rtc_state, i, bits);
bits = ~bits;
}
bits = 0x55;
for (i = 0x80; i < 0x100; i++) {
rtc_set_memory(rtc_state, i, bits);
bits = ~bits;
}
/* smbus devices */
uint8_t *eeprom_buf = g_malloc0(256);
memcpy(eeprom_buf, eeprom, 256);
smbus_eeprom_init_one(smbus, 0x54, eeprom_buf);
smbus_xbox_smc_init(smbus, 0x10);
smbus_cx25871_init(smbus, 0x45);
smbus_adm1032_init(smbus, 0x4c);
/* USB */
PCIDevice *usb1 = pci_create(pci_bus, PCI_DEVFN(3, 0), "pci-ohci");
qdev_prop_set_uint32(&usb1->qdev, "num-ports", 4);
qdev_init_nofail(&usb1->qdev);
PCIDevice *usb0 = pci_create(pci_bus, PCI_DEVFN(2, 0), "pci-ohci");
qdev_prop_set_uint32(&usb0->qdev, "num-ports", 4);
qdev_init_nofail(&usb0->qdev);
/* Ethernet! */
PCIDevice *nvnet = pci_create(pci_bus, PCI_DEVFN(4, 0), "nvnet");
for (i = 0; i < nb_nics; i++) {
NICInfo *nd = &nd_table[i];
qemu_check_nic_model(nd, "nvnet");
qdev_set_nic_properties(&nvnet->qdev, nd);
qdev_init_nofail(&nvnet->qdev);
}
/* APU! */
mcpx_apu_init(pci_bus, PCI_DEVFN(5, 0), ram_memory);
/* ACI! */
pci_create_simple(pci_bus, PCI_DEVFN(6, 0), "mcpx-aci");
/* GPU! */
nv2a_init(agp_bus, PCI_DEVFN(0, 0), ram_memory);
if (pci_bus_out) {
*pci_bus_out = pci_bus;
}
if (isa_bus_out) {
*isa_bus_out = isa_bus;
}
}
static void at91sam9_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *kernel_cmdline,
const char *initrd_filename,
const char *cpu_model)
{
CPUState *env;
DriveInfo *dinfo;
struct at91sam9_state *sam9;
int iomemtype;
qemu_irq *cpu_pic;
qemu_irq pic[32];
qemu_irq pic1[32];
DeviceState *dev;
DeviceState *pit;
DeviceState *pmc;
DeviceState *spi;
int i;
int bms;
SPIControl *cs0_spi_handler;
cs0_spi_handler = qemu_mallocz(sizeof(SPIControl));
DEBUG("begin, ram_size %llu, boot dev %s\n", (unsigned long long)ram_size,
boot_device ? boot_device : "<empty>");
if (option_rom[0] && boot_device[0] == 'n') {
printf("Emulate ROM code\n");
bms = 1;
} else {
printf("Emulate start from EBI0_NCS0\n");
bms = 0;
}
#ifdef TRACE_ON
trace_file = fopen("/tmp/trace.log", "w");
#endif
if (!cpu_model)
cpu_model = "arm926";
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(EXIT_FAILURE);
}
/* SDRAM at chipselect 1. */
cpu_register_physical_memory(AT91SAM9263EK_SDRAM_OFF, AT91SAM9263EK_SDRAM_SIZE,
qemu_ram_alloc(AT91SAM9263EK_SDRAM_SIZE) | IO_MEM_RAM);
sam9 = (struct at91sam9_state *)qemu_mallocz(sizeof(*sam9));
if (!sam9) {
fprintf(stderr, "allocation failed\n");
exit(EXIT_FAILURE);
}
sam9->env = env;
/* Internal SRAM */
sam9->internal_sram = qemu_ram_alloc(80 * 1024);
cpu_register_physical_memory(0x00300000, 80 * 1024, sam9->internal_sram | IO_MEM_RAM);
sam9->bootrom = qemu_ram_alloc(0x100000);
cpu_register_physical_memory(0x00400000, 0x100000, sam9->bootrom | IO_MEM_RAM);
if (option_rom[0]) {
sam9->rom_size = load_image_targphys(option_rom[0], 0x00400000, 0x100000);
printf("load bootrom, size %d\n", sam9->rom_size);
}
/*Internal Peripherals */
iomemtype = cpu_register_io_memory(at91_periph_readfn, at91_periph_writefn, sam9);
cpu_register_physical_memory(0xF0000000, 0xFFFFFFFF - 0xF0000000, iomemtype);
cpu_pic = arm_pic_init_cpu(env);
dev = sysbus_create_varargs("at91,aic", AT91_AIC_BASE,
cpu_pic[ARM_PIC_CPU_IRQ],
cpu_pic[ARM_PIC_CPU_FIQ],
NULL);
for (i = 0; i < 32; i++) {
pic[i] = qdev_get_gpio_in(dev, i);
}
dev = sysbus_create_simple("at91,intor", -1, pic[1]);
for (i = 0; i < 32; i++) {
pic1[i] = qdev_get_gpio_in(dev, i);
}
sysbus_create_simple("at91,dbgu", AT91_DBGU_BASE, pic1[0]);
pmc = sysbus_create_simple("at91,pmc", AT91_PMC_BASE, pic1[1]);
qdev_prop_set_uint32(pmc, "mo_freq", 16000000);
pit = sysbus_create_simple("at91,pit", AT91_PITC_BASE, pic1[3]);
sysbus_create_varargs("at91,tc", AT91_TC012_BASE, pic[19], pic[19], pic[19], NULL);
spi = sysbus_create_simple("at91,spi", AT91_SPI0_BASE, pic[14]);
at91_init_bus_matrix(sam9);
memset(&sam9->ccfg_regs, 0, sizeof(sam9->ccfg_regs));
sysbus_create_simple("at91,pio", AT91_PIOA_BASE, pic[2]);
sysbus_create_simple("at91,pio", AT91_PIOB_BASE, pic[3]);
sysbus_create_simple("at91,pio", AT91_PIOC_BASE, pic[4]);
sysbus_create_simple("at91,pio", AT91_PIOD_BASE, pic[4]);
sysbus_create_simple("at91,pio", AT91_PIOE_BASE, pic[4]);
sysbus_create_varargs("at91,rstc", AT91_RSTC_BASE, NULL);
memset(&sam9->sdramc0_regs, 0, sizeof(sam9->sdramc0_regs));
memset(&sam9->smc0_regs, 0, sizeof(sam9->smc0_regs));
memset(sam9->usart0_regs, 0, sizeof(sam9->usart0_regs));
qemu_check_nic_model(&nd_table[0], "at91");
dev = qdev_create(NULL, "at91,emac");
dev->nd = &nd_table[0];
qdev_init(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, AT91_EMAC_BASE);
sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[21]);
sysbus_create_simple("at91,lcdc", AT91_LCDC_BASE, pic[26]);
/*
we use variant of booting from external memory (NOR FLASH),
it mapped to 0x0 at start, and also it is accessable from 0x10000000 address
*/
dinfo = drive_get(IF_PFLASH, 0, 0);
if (dinfo) {
if (bms) {
NANDFlashState *nand_state;
if (spi_flash_register(dinfo->bdrv, 4 * 1024 * 1024, cs0_spi_handler) < 0) {
fprintf(stderr, "init of spi flash failed\n");
exit(EXIT_FAILURE);
}
qdev_prop_set_ptr(spi, "spi_control", cs0_spi_handler);
//rom
cpu_register_physical_memory(0x0, 100 * 1024,
sam9->bootrom | IO_MEM_ROMD);
nand_state = nand_init(NAND_MFR_MICRON, 0xba);
at91_nand_register(nand_state);
} else {
//nor flash
ram_addr_t nor_flash_mem = qemu_ram_alloc(NOR_FLASH_SIZE);
if (!nor_flash_mem) {
fprintf(stderr, "allocation failed\n");
exit(EXIT_FAILURE);
}
sam9->norflash = pflash_cfi_atmel_register(AT91SAM9263EK_NORFLASH_OFF,
nor_flash_mem,
dinfo->bdrv,
4 * 1024 * 2, 8,
32 * 1024 * 2,
(135 - 8),
2, 0x001F, 0x01D6, 0, 0);
if (!sam9->norflash) {
fprintf(stderr, "qemu: error registering flash memory.\n");
exit(EXIT_FAILURE);
}
DEBUG("register flash at 0x0\n");
//register only part of flash, to prevent conflict with internal sram
cpu_register_physical_memory(0x0, 100 * 1024,
nor_flash_mem | IO_MEM_ROMD);
}
} else {
fprintf(stderr, "qemu: can not start without flash.\n");
exit(EXIT_FAILURE);
}
g_env = env;
env->regs[15] = 0x0;
}
static void
petalogix_ml605_init(QEMUMachineInitArgs *args)
{
ram_addr_t ram_size = args->ram_size;
const char *cpu_model = args->cpu_model;
MemoryRegion *address_space_mem = get_system_memory();
DeviceState *dev, *dma, *eth0;
MicroBlazeCPU *cpu;
SysBusDevice *busdev;
CPUMBState *env;
DriveInfo *dinfo;
int i;
hwaddr ddr_base = MEMORY_BASEADDR;
MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
if (cpu_model == NULL) {
cpu_model = "microblaze";
}
cpu = cpu_mb_init(cpu_model);
env = &cpu->env;
/* Attach emulated BRAM through the LMB. */
memory_region_init_ram(phys_lmb_bram, "petalogix_ml605.lmb_bram",
LMB_BRAM_SIZE);
vmstate_register_ram_global(phys_lmb_bram);
memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram);
memory_region_init_ram(phys_ram, "petalogix_ml605.ram", ram_size);
vmstate_register_ram_global(phys_ram);
memory_region_add_subregion(address_space_mem, ddr_base, phys_ram);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0);
cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 4);
for (i = 0; i < 32; i++) {
irq[i] = qdev_get_gpio_in(dev, i);
}
serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2,
irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN);
/* 2 timers at irq 2 @ 100 Mhz. */
xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000);
/* axi ethernet and dma initialization. */
qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet");
eth0 = qdev_create(NULL, "xlnx.axi-ethernet");
dma = qdev_create(NULL, "xlnx.axi-dma");
/* FIXME: attach to the sysbus instead */
object_property_add_child(container_get(qdev_get_machine(), "/unattached"),
"xilinx-dma", OBJECT(dma), NULL);
xilinx_axiethernet_init(eth0, &nd_table[0], STREAM_SLAVE(dma),
0x82780000, irq[3], 0x1000, 0x1000);
xilinx_axidma_init(dma, STREAM_SLAVE(eth0), 0x84600000, irq[1], irq[0],
100 * 1000000);
{
SSIBus *spi;
dev = qdev_create(NULL, "xlnx.xps-spi");
qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES);
qdev_init_nofail(dev);
busdev = SYS_BUS_DEVICE(dev);
sysbus_mmio_map(busdev, 0, 0x40a00000);
sysbus_connect_irq(busdev, 0, irq[4]);
spi = (SSIBus *)qdev_get_child_bus(dev, "spi");
for (i = 0; i < NUM_SPI_FLASHES; i++) {
qemu_irq cs_line;
dev = ssi_create_slave_no_init(spi, "m25p80");
qdev_prop_set_string(dev, "partname", "n25q128");
qdev_init_nofail(dev);
cs_line = qdev_get_gpio_in(dev, 0);
sysbus_connect_irq(busdev, i+1, cs_line);
}
}
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
}