int qm_spi_dma_transfer_terminate(qm_spi_t spi)
{
QM_CHECK(spi < QM_SPI_NUM, -EINVAL);
QM_CHECK(dma_context_tx[spi].cb_pending
? (dma_context_tx[spi].dma_channel_id < QM_DMA_CHANNEL_NUM)
: 1,
-EINVAL);
QM_CHECK(dma_context_rx[spi].cb_pending
? (dma_context_rx[spi].dma_channel_id < QM_DMA_CHANNEL_NUM)
: 1,
-EINVAL);
int ret = 0;
if (dma_context_tx[spi].cb_pending) {
if (0 !=
qm_dma_transfer_terminate(
dma_core[spi], dma_context_tx[spi].dma_channel_id)) {
ret = -EIO;
}
}
if (dma_context_rx[spi].cb_pending) {
if (0 !=
qm_dma_transfer_terminate(
dma_core[spi], dma_context_rx[spi].dma_channel_id)) {
ret = -EIO;
}
}
return ret;
}
/* Do NUM_TRANSFERS DMA transfers. */
static void do_transfer(dma_channel_desc_t *p_chan_desc)
{
#if (QM_SENSOR)
uint32_t t_init;
#else
uint64_t t_init;
#endif
int return_code;
QM_PUTS("Starting the transfer and waiting for 1 second.");
/* Get system tick time. */
t_init = get_ticks();
/* Start first transfer. */
start_transfer(p_chan_desc, (uint32_t *)tx_data,
(uint32_t *)rx_data[transfer_count], strlen(tx_data));
/*
* Loop until 1 second has elapsed from start or
* NUM_TRANSFERS transfers are finished.
*/
while (((get_ticks() - t_init) < SYS_TICKS_PER_S_32MHZ) &&
(transfer_count < NUM_TRANSFERS)) {
if (irq_fired) {
irq_fired = false;
start_another_transfer(p_chan_desc);
}
}
/* If the transfer has not finished then stop the channel. */
if (transfer_count < NUM_TRANSFERS) {
return_code = qm_dma_transfer_terminate(
p_chan_desc->controller_id, p_chan_desc->channel_id);
if (return_code) {
QM_PUTS("ERROR: qm_dma_transfer_stop");
}
}
}
static int dma_qmsi_stop(struct device *dev, u32_t channel)
{
const struct dma_qmsi_config_info *info = dev->config->config_info;
return qm_dma_transfer_terminate(info->instance, channel);
}
