void boot_sense_jtag_probe(void)
{
/* Hardware default (sticky):
* - clock gating:
* - QM_CLK_PERIPH_REGISTER and QM_CLK_PERIPH_GPIO_REGISTER enabled
* - QM_CLK_PERIPH_CLK disabled
* - pin muxing
* - gpio's muxed out
* - input pads enabled
* - pad pullup disabled
* - gpio port configured as input
*/
qm_gpio_state_t state;
qm_pmux_pullup_en(WAIT_FOR_JTAG_PAD, true);
qm_pmux_select(WAIT_FOR_JTAG_PAD, QM_PMUX_FN_0);
qm_pmux_input_en(WAIT_FOR_JTAG_PAD, true);
clk_periph_enable(CLK_PERIPH_REGISTER | CLK_PERIPH_CLK |
CLK_PERIPH_GPIO_REGISTER);
do {
/* Busy loop to allow JTAG access */
qm_gpio_read_pin(QM_GPIO_0, WAIT_FOR_JTAG_GPIO, &state);
} while (state == QM_GPIO_LOW);
/* Restore hardware default settings */
clk_periph_disable(CLK_PERIPH_CLK);
qm_pmux_pullup_en(WAIT_FOR_JTAG_PAD, false);
};
static int pinmux_dev_input(struct device *dev, uint32_t pin,
uint8_t func)
{
ARG_UNUSED(dev);
return qm_pmux_input_en(pin, func) == QM_RC_OK ? 0 : -EIO;
}
int main(void)
{
/* Comparator example app
*
* This app sets up comparator 0 to fire an interrupt when the input
* voltage is greater than the reference voltage (0.95V)
*
* On the Intel(R) Quark(TM) Microcontroller D2000 Development Platform
* the pin used is marked "SSO 10"
*/
qm_ac_config_t ac_cfg;
QM_PUTS("Analog Comparators example app start\n");
/* Set up pin muxing and request IRQ*/
qm_pmux_select(QM_PIN_ID_0, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_0, true);
qm_irq_request(QM_IRQ_AC, qm_ac_isr);
/* Write configs */
ac_cfg.reference = BIT(0); /* Ref internal voltage */
ac_cfg.polarity = 0x0; /* Fire if greater than ref (high level) */
ac_cfg.power = BIT(0); /* Normal operation mode */
ac_cfg.int_en = BIT(0); /* AIN0 enable */
ac_cfg.callback = ac_example_callback;
qm_ac_set_config(&ac_cfg);
QM_PUTS("Analog Comparators example app complete\n");
return 0;
}
static void deep_sleep_test(void)
{
/*
* Setup the RTC to get out of sleep mode. deep sleep will require an
* analog comparator interrupt to wake up the system.
*/
uint32_t pmux_sel_save[2], pmux_in_en_save, pmux_pullup_save;
qm_ac_config_t ac_cfg;
/*
* Physical step at this stage to raise the V on the comparator
* pin.
*
* Go to deep sleep, a comparator should wake me up.
*/
ac_cfg.reference =
BIT(WAKEUP_COMPARATOR_PIN); /* Ref internal voltage. */
ac_cfg.polarity = 0x0; /* Fire if greater than ref (high level). */
ac_cfg.power = BIT(WAKEUP_COMPARATOR_PIN); /* Normal operation mode. */
ac_cfg.int_en = BIT(WAKEUP_COMPARATOR_PIN); /* Enable comparator. */
ac_cfg.callback = ac_example_callback;
qm_ac_set_config(&ac_cfg);
qm_irq_request(QM_IRQ_COMPARATOR_0_INT, qm_comparator_0_isr);
/*
* Comparator pin will fire an interrupt when the input voltage
* is greater than the reference voltage (0.95V).
*/
/*
* In order to minimise power, pmux_sel must be set to 0, input
* enable must be cleared for any pins not expecting to be
* used to wake the SoC from deep sleep mode, in this example
* we are using AC 6.
*/
pmux_sel_save[0] = QM_SCSS_PMUX->pmux_sel[0];
pmux_sel_save[1] = QM_SCSS_PMUX->pmux_sel[1];
pmux_in_en_save = QM_SCSS_PMUX->pmux_in_en[0];
pmux_pullup_save = QM_SCSS_PMUX->pmux_pullup[0];
QM_SCSS_PMUX->pmux_sel[0] = QM_SCSS_PMUX->pmux_sel[1] = 0;
QM_SCSS_PMUX->pmux_in_en[0] = BIT(WAKEUP_COMPARATOR_PIN);
QM_SCSS_PMUX->pmux_pullup[0] = 0;
/* Mux out comparator. */
qm_pmux_select(QM_PIN_ID_6, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_6, true);
ENTER_C2LP();
/* Restore previous pinmuxing settings. */
QM_SCSS_PMUX->pmux_sel[0] = pmux_sel_save[0];
QM_SCSS_PMUX->pmux_sel[1] = pmux_sel_save[1];
QM_SCSS_PMUX->pmux_in_en[0] = pmux_in_en_save;
QM_SCSS_PMUX->pmux_pullup[0] = pmux_pullup_save;
}
static void pin_mux_setup(void)
{
/* Set GPIO mux mode. */
qm_pmux_pullup_en(QM_PIN_ID_11, true);
qm_pmux_select(QM_PIN_ID_11, QM_PIN_11_FN_GPIO_SS_3);
qm_pmux_select(QM_PIN_ID_10, QM_PIN_10_FN_GPIO_SS_2);
/* Enable input on PIN_INTR. */
qm_pmux_input_en(QM_PIN_ID_11, true);
}
/*-------------------------------------------------------------------------*/
void xmodem_io_uart_init()
{
/* Pinmux for UART_x */
qm_pmux_select(DM_COMM_UART_PIN_TX_ID, DM_COMM_UART_PIN_TX_FN);
qm_pmux_select(DM_COMM_UART_PIN_RX_ID, DM_COMM_UART_PIN_RX_FN);
qm_pmux_input_en(DM_COMM_UART_PIN_RX_ID, true);
/* Enable UART and RTC clocks */
clk_periph_enable(DM_COMM_UART_CLK | CLK_PERIPH_RTC_REGISTER |
CLK_PERIPH_CLK);
/* Setup UART */
qm_uart_set_config(DM_CONFIG_UART, &uart_config);
/* Request IRQ for UART */
dm_comm_irq_request();
/* Set up timeout timer (RTC) */
qm_irq_request(QM_IRQ_RTC_0, qm_rtc_isr_0);
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
}
int main(void)
{
#if (QUARK_D2000)
int i;
qm_adc_config_t cfg;
qm_adc_xfer_t xfer;
qm_adc_channel_t channels[] = {QM_ADC_CH_8, QM_ADC_CH_9};
uint32_t samples_polled[NUM_SAMPLES_POLLED] = {0};
uint32_t samples_interrupt[NUM_SAMPLES_INTERRUPT] = {0};
QM_PUTS("\nADC example app start");
/* Enable the ADC and set the clock divisor */
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_ADC |
CLK_PERIPH_ADC_REGISTER);
clk_adc_set_div(100); /* ADC clock is 320KHz @ 32MHz */
/* Set up pinmux */
qm_pmux_select(QM_PIN_ID_8, QM_PMUX_FN_1);
qm_pmux_select(QM_PIN_ID_9, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_8, true);
qm_pmux_input_en(QM_PIN_ID_9, true);
/* Set the mode and calibrate */
qm_adc_set_mode(QM_ADC_0, QM_ADC_MODE_NORM_CAL);
qm_adc_calibrate(QM_ADC_0);
/* Set up config */
cfg.window = 20; /* Clock cycles between the start of each sample */
cfg.resolution = QM_ADC_RES_12_BITS;
qm_adc_set_config(QM_ADC_0, &cfg);
/*******************************
* ADC polled mode example
******************************/
QM_PUTS("ADC polled mode");
/* Set up xfer */
xfer.ch = channels;
xfer.ch_len = NUM_CHANNELS;
xfer.samples = samples_polled;
xfer.samples_len = NUM_SAMPLES_POLLED;
/* Run the conversion */
if (qm_adc_convert(QM_ADC_0, &xfer)) {
QM_PUTS("ERROR: qm_adc_convert failed");
return 1;
}
/* Print the values of the samples */
for (i = 0; i < NUM_SAMPLES_POLLED; i++) {
QM_PRINTF("%d:%x ", i, (unsigned int)samples_polled[i]);
}
/*******************************
* ADC interrupt mode example
******************************/
QM_PUTS("\nADC interrupt mode");
qm_irq_request(QM_IRQ_ADC_0, qm_adc_0_isr);
/* Set up xfer */
xfer.ch = channels;
xfer.ch_len = NUM_CHANNELS;
xfer.samples = samples_interrupt;
xfer.samples_len = NUM_SAMPLES_INTERRUPT;
xfer.complete_callback = complete_callback;
xfer.error_callback = error_callback;
if (qm_adc_irq_convert(QM_ADC_0, &xfer)) {
QM_PUTS("ERROR: qm_adc_irq_convert failed");
return 1;
}
/* Wait for the callback */
while (false == complete)
;
for (i = 0; i < NUM_SAMPLES_INTERRUPT; i++) {
QM_PRINTF("%d:%x ", i, (unsigned int)samples_interrupt[i]);
}
QM_PUTS("\nADC example app complete");
#endif /* QUARK_D2000 */
return 0;
}
/* Low power app example */
int main(void)
{
/* Setup the RTC to get out of sleep mode. deep sleep will require an */
/* analog comparator interrupt to wake up the system. */
/* Variables */
uint32_t pmux_sel_save[2], pmux_in_en_save, pmux_pullup_save;
qm_ac_config_t ac_cfg;
qm_rtc_config_t rtc_cfg;
QM_PUTS("Low power mode example.");
clk_periph_enable(CLK_PERIPH_RTC_REGISTER | CLK_PERIPH_CLK);
/* Initialise RTC configuration. */
rtc_cfg.init_val = 0;
rtc_cfg.alarm_en = 1;
rtc_cfg.alarm_val = QM_RTC_ALARM_SECOND;
rtc_cfg.callback = rtc_example_callback;
qm_rtc_set_config(QM_RTC_0, &rtc_cfg);
qm_irq_request(QM_IRQ_RTC_0, qm_rtc_isr_0);
QM_PUTS("CPU Halt.");
/* Halt the CPU, RTC alarm will wake me up. */
cpu_halt();
QM_PUTS("CPU Halt wakeup.");
/* Set another alarm one minute from now. */
qm_rtc_set_alarm(QM_RTC_0,
QM_RTC[QM_RTC_0].rtc_ccvr + QM_RTC_ALARM_SECOND);
QM_PUTS("Go to sleep.");
/* Go to sleep, RTC will wake me up. */
soc_sleep();
QM_PUTS("Wake up from sleep.");
/* Physical step at this stage to raise the V on the comparator pin. */
/* Go to deep sleep, a comparator should wake me up. */
QM_PUTS("Go to deep sleep.");
ac_cfg.reference =
BIT(WAKEUP_COMPARATOR_PIN); /* Ref internal voltage */
ac_cfg.polarity = 0x0; /* Fire if greater than ref (high level) */
ac_cfg.power = BIT(WAKEUP_COMPARATOR_PIN); /* Normal operation mode */
ac_cfg.int_en = BIT(WAKEUP_COMPARATOR_PIN); /* Enable comparator */
ac_cfg.callback = ac_example_callback;
qm_ac_set_config(&ac_cfg);
qm_irq_request(QM_IRQ_AC, qm_ac_isr);
/*
* Comparator pin will fire an interrupt when the input voltage is
* greater than the reference voltage (0.95V).
*/
/*
* In order to minimise power, pmux_sel must be set to 0, input enable
* must be cleared for any pins not expecting to be used to wake the
* SoC from deep sleep mode, in this example we are using AC 6.
*/
pmux_sel_save[0] = QM_SCSS_PMUX->pmux_sel[0];
pmux_sel_save[1] = QM_SCSS_PMUX->pmux_sel[1];
pmux_in_en_save = QM_SCSS_PMUX->pmux_in_en[0];
pmux_pullup_save = QM_SCSS_PMUX->pmux_pullup[0];
QM_SCSS_PMUX->pmux_sel[0] = QM_SCSS_PMUX->pmux_sel[1] = 0;
QM_SCSS_PMUX->pmux_in_en[0] = BIT(WAKEUP_COMPARATOR_PIN);
QM_SCSS_PMUX->pmux_pullup[0] = 0;
/* Mux out comparator */
qm_pmux_select(QM_PIN_ID_6, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_6, true);
soc_deep_sleep();
/* Restore previous pinmuxing settings. */
QM_SCSS_PMUX->pmux_sel[0] = pmux_sel_save[0];
QM_SCSS_PMUX->pmux_sel[1] = pmux_sel_save[1];
QM_SCSS_PMUX->pmux_in_en[0] = pmux_in_en_save;
QM_SCSS_PMUX->pmux_pullup[0] = pmux_pullup_save;
QM_PUTS("Wake up from deep sleep.");
return 0;
}
/* QMSI SPI app example */
int main(void)
{
/* Variables */
qm_spi_config_t cfg;
qm_spi_transfer_t polled_xfer_desc;
qm_spi_async_transfer_t irq_xfer_desc;
unsigned int i;
for (i = 0; i < BUFFERSIZE; i++) {
tx_buff[i] = i;
}
/* Mux out SPI tx/rx pins and enable input for rx. */
#if (QUARK_SE)
qm_pmux_select(QM_PIN_ID_55, QM_PMUX_FN_1); /* SPI0_M SCK */
qm_pmux_select(QM_PIN_ID_56, QM_PMUX_FN_1); /* SPI0_M MISO */
qm_pmux_select(QM_PIN_ID_57, QM_PMUX_FN_1); /* SPI0_M MOSI */
qm_pmux_select(QM_PIN_ID_58, QM_PMUX_FN_1); /* SPI0_M SS0 */
qm_pmux_select(QM_PIN_ID_59, QM_PMUX_FN_1); /* SPI0_M SS1 */
qm_pmux_select(QM_PIN_ID_60, QM_PMUX_FN_1); /* SPI0_M SS2 */
qm_pmux_select(QM_PIN_ID_61, QM_PMUX_FN_1); /* SPI0_M SS3 */
qm_pmux_input_en(QM_PIN_ID_56, true);
#elif(QUARK_D2000)
qm_pmux_select(QM_PIN_ID_0, QM_PMUX_FN_2); /* SS0 */
qm_pmux_select(QM_PIN_ID_1, QM_PMUX_FN_2); /* SS1 */
qm_pmux_select(QM_PIN_ID_2, QM_PMUX_FN_2); /* SS2 */
qm_pmux_select(QM_PIN_ID_3, QM_PMUX_FN_2); /* SS3 */
qm_pmux_select(QM_PIN_ID_16, QM_PMUX_FN_2); /* SCK */
qm_pmux_select(QM_PIN_ID_17, QM_PMUX_FN_2); /* TXD */
qm_pmux_select(QM_PIN_ID_18, QM_PMUX_FN_2); /* RXD */
qm_pmux_input_en(QM_PIN_ID_18, true); /* RXD input */
#else
#error("Unsupported / unspecified processor detected.")
#endif
/* Enable the clock to the controller. */
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
/* Initialise SPI configuration */
cfg.frame_size = QM_SPI_FRAME_SIZE_8_BIT;
cfg.transfer_mode = QM_SPI_TMOD_TX_RX;
cfg.bus_mode = QM_SPI_BMODE_0;
cfg.clk_divider = SPI_CLOCK_DIV;
qm_spi_set_config(QM_SPI_MST_0, &cfg);
/* Set up loopback mode by RMW directly to the ctrlr0 register. */
QM_SPI[QM_SPI_MST_0]->ctrlr0 |= BIT(11);
qm_spi_slave_select(QM_SPI_MST_0, QM_SPI_SS_0);
QM_PRINTF("\nStatus = 0x%08x", qm_spi_get_status(QM_SPI_MST_0));
/* Set up the sync transfer struct and call a polled transfer. */
polled_xfer_desc.tx = tx_buff;
polled_xfer_desc.rx = rx_buff;
polled_xfer_desc.tx_len = BUFFERSIZE;
polled_xfer_desc.rx_len = BUFFERSIZE;
qm_spi_transfer(QM_SPI_MST_0, &polled_xfer_desc);
/* Compare RX and TX buffers */
/* Also reset the buffers for the IRQ example */
for (i = 0; i < BUFFERSIZE; i++) {
QM_CHECK(tx_buff[i] == rx_buff[i], QM_RC_EINVAL);
tx_buff[i] = i;
rx_buff[i] = 0;
}
/* Set up the async transfer struct. */
irq_xfer_desc.tx = tx_buff;
irq_xfer_desc.rx = rx_buff;
irq_xfer_desc.tx_len = BUFFERSIZE;
irq_xfer_desc.rx_len = BUFFERSIZE;
irq_xfer_desc.id = SPI_EXAMPLE_IRQ_ID;
irq_xfer_desc.rx_callback = spi_rx_example_cb;
irq_xfer_desc.tx_callback = spi_tx_example_cb;
irq_xfer_desc.err_callback = spi_err_example_cb;
/* Register driver IRQ. */
qm_irq_request(QM_IRQ_SPI_MASTER_0, qm_spi_master_0_isr);
/* Start the async (irq-based) transfer. */
qm_spi_irq_transfer(QM_SPI_MST_0, &irq_xfer_desc);
while (1)
;
return 0;
}
/* Sample UART0 QMSI application. */
int main(void)
{
qm_uart_config_t cfg = {0};
qm_uart_status_t uart_status __attribute__((unused)) = 0;
int ret __attribute__((unused));
const uint32_t xfer_irq_data = BANNER_IRQ_ID;
const uint32_t xfer_dma_data = BANNER_DMA_ID;
/* Set divisors to yield 115200bps baud rate. */
/* Sysclk is set by boot ROM to hybrid osc in crystal mode (32MHz),
* peripheral clock divisor set to 1.
*/
cfg.baud_divisor = QM_UART_CFG_BAUD_DL_PACK(0, 17, 6);
cfg.line_control = QM_UART_LC_8N1;
cfg.hw_fc = false;
/* Mux out STDOUT_UART tx/rx pins and enable input for rx. */
#if (QUARK_SE)
if (STDOUT_UART == QM_UART_0) {
qm_pmux_select(QM_PIN_ID_18, QM_PMUX_FN_0);
qm_pmux_select(QM_PIN_ID_19, QM_PMUX_FN_0);
qm_pmux_input_en(QM_PIN_ID_18, true);
} else {
qm_pmux_select(QM_PIN_ID_16, QM_PMUX_FN_2);
qm_pmux_select(QM_PIN_ID_17, QM_PMUX_FN_2);
qm_pmux_input_en(QM_PIN_ID_17, true);
}
#elif(QUARK_D2000)
if (STDOUT_UART == QM_UART_0) {
qm_pmux_select(QM_PIN_ID_12, QM_PMUX_FN_2);
qm_pmux_select(QM_PIN_ID_13, QM_PMUX_FN_2);
qm_pmux_input_en(QM_PIN_ID_13, true);
} else {
qm_pmux_select(QM_PIN_ID_20, QM_PMUX_FN_2);
qm_pmux_select(QM_PIN_ID_21, QM_PMUX_FN_2);
qm_pmux_input_en(QM_PIN_ID_21, true);
}
#else
#error("Unsupported / unspecified processor detected.")
#endif
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_UARTA_REGISTER);
qm_uart_set_config(STDOUT_UART, &cfg);
QM_PRINTF("Starting: UART\n");
/* Synchronous TX. */
ret = qm_uart_write_buffer(STDOUT_UART, (uint8_t *)BANNER_STR,
sizeof(BANNER_STR));
QM_ASSERT(0 == ret);
/* Register the UART interrupts. */
#if (STDOUT_UART_0)
qm_irq_request(QM_IRQ_UART_0, qm_uart_0_isr);
#elif(STDOUT_UART_1)
qm_irq_request(QM_IRQ_UART_1, qm_uart_1_isr);
#endif
/* Used on both TX and RX. */
async_xfer_desc.callback_data = (void *)&xfer_irq_data;
/* IRQ based TX. */
async_xfer_desc.data = (uint8_t *)BANNER_IRQ;
async_xfer_desc.data_len = sizeof(BANNER_IRQ);
async_xfer_desc.callback = uart_example_tx_callback;
ret = qm_uart_irq_write(STDOUT_UART, &async_xfer_desc);
QM_ASSERT(0 == ret);
clk_sys_udelay(WAIT_1SEC);
/* IRQ based RX. */
rx_callback_invoked = false;
async_xfer_desc.data = rx_buffer;
async_xfer_desc.data_len = BIG_NUMBER_RX;
async_xfer_desc.callback = uart_example_rx_callback;
ret = qm_uart_irq_read(STDOUT_UART, &async_xfer_desc);
QM_ASSERT(0 == ret);
QM_PRINTF("\nWaiting for you to type %d characters... ?\n",
BIG_NUMBER_RX);
wait_rx_callback_timeout(TIMEOUT_10SEC);
if (!rx_callback_invoked) {
/* RX complete callback was not invoked, we need to terminate
* the transfer in order to grab whatever is available in the RX
* buffer. */
ret = qm_uart_irq_read_terminate(STDOUT_UART);
QM_ASSERT(0 == ret);
} else {
/* RX complete callback was invoked and RX buffer was read, we
* wait in case the user does not stop typing after entering the
* exact amount of data that fits the RX buffer, i.e. there may
* be additional bytes in the RX FIFO that need to be read
* before continuing. */
clk_sys_udelay(WAIT_5SEC);
qm_uart_get_status(STDOUT_UART, &uart_status);
if (QM_UART_RX_BUSY & uart_status) {
/* There is some data in the RX FIFO, let's fetch it. */
ret = qm_uart_irq_read(STDOUT_UART, &async_xfer_desc);
QM_ASSERT(0 == ret);
ret = qm_uart_irq_read_terminate(STDOUT_UART);
QM_ASSERT(0 == ret);
}
}
/* Register the DMA interrupts. */
qm_irq_request(QM_IRQ_DMA_0, qm_dma_0_isr_0);
qm_irq_request(QM_IRQ_DMA_ERR, qm_dma_0_isr_err);
/* DMA controller initialization. */
ret = qm_dma_init(QM_DMA_0);
QM_ASSERT(0 == ret);
/* Used on both TX and RX. */
async_xfer_desc.callback_data = (void *)&xfer_dma_data;
/* DMA based TX. */
ret =
qm_uart_dma_channel_config(STDOUT_UART, QM_DMA_0, QM_DMA_CHANNEL_0,
QM_DMA_MEMORY_TO_PERIPHERAL);
QM_ASSERT(0 == ret);
async_xfer_desc.data = (uint8_t *)BANNER_DMA;
async_xfer_desc.data_len = sizeof(BANNER_DMA);
async_xfer_desc.callback = uart_example_tx_callback;
ret = qm_uart_dma_write(STDOUT_UART, &async_xfer_desc);
QM_ASSERT(0 == ret);
clk_sys_udelay(WAIT_1SEC);
/* DMA based RX. */
rx_callback_invoked = false;
ret =
qm_uart_dma_channel_config(STDOUT_UART, QM_DMA_0, QM_DMA_CHANNEL_0,
QM_DMA_PERIPHERAL_TO_MEMORY);
QM_ASSERT(0 == ret);
QM_PUTS("Waiting for data on STDOUT_UART (DMA mode) ...");
async_xfer_desc.data = (uint8_t *)rx_buffer;
async_xfer_desc.data_len = BIG_NUMBER_RX;
async_xfer_desc.callback = uart_example_rx_callback;
ret = qm_uart_dma_read(STDOUT_UART, &async_xfer_desc);
QM_ASSERT(0 == ret);
wait_rx_callback_timeout(TIMEOUT_10SEC);
if (!rx_callback_invoked) {
/* RX complete callback was not invoked, we need to terminate
* the transfer in order to grab whatever was written in the RX
* buffer. */
ret = qm_uart_dma_read_terminate(STDOUT_UART);
QM_ASSERT(0 == ret);
}
QM_PRINTF("\nFinished: UART\n");
return 0;
}
int main(void)
{
int i;
qm_ss_adc_config_t cfg;
qm_ss_adc_xfer_t xfer;
qm_ss_adc_channel_t channels[] = {QM_SS_ADC_CH_10, QM_SS_ADC_CH_11};
uint16_t samples_polled[NUM_SAMPLES_POLLED] = {0};
uint16_t samples_interrupt[NUM_SAMPLES_INTERRUPT] = {0};
QM_PUTS("Starting: SS ADC");
/* Enable the ADC and set the clock divisor. */
ss_clk_adc_enable();
ss_clk_adc_set_div(100);
/* Set up pinmux. */
qm_pmux_select(QM_PIN_ID_10, QM_PMUX_FN_1);
qm_pmux_select(QM_PIN_ID_11, QM_PMUX_FN_1);
qm_pmux_input_en(QM_PIN_ID_10, true);
qm_pmux_input_en(QM_PIN_ID_11, true);
/* Set the mode and calibrate. */
qm_ss_adc_set_mode(QM_SS_ADC_0, QM_SS_ADC_MODE_NORM_CAL);
qm_ss_adc_calibrate(QM_SS_ADC_0);
/* Set up config. */
cfg.window = 50; /* Clock cycles between the start of each sample. */
cfg.resolution = QM_SS_ADC_RES_12_BITS;
qm_ss_adc_set_config(QM_SS_ADC_0, &cfg);
/* ADC polled mode example. */
QM_PUTS("ADC polled mode");
/* Set up xfer. */
xfer.ch = channels;
xfer.ch_len = NUM_CHANNELS;
xfer.samples = samples_polled;
xfer.samples_len = NUM_SAMPLES_POLLED;
xfer.callback = NULL;
xfer.callback_data = NULL;
/* Run the conversion. */
if (qm_ss_adc_convert(QM_SS_ADC_0, &xfer, NULL)) {
QM_PUTS("Error: qm_ss_adc_convert failed");
return 1;
}
/* Print the values of the samples. */
for (i = 0; i < NUM_SAMPLES_POLLED; i++) {
QM_PRINTF("%d:%x ", i, (unsigned int)samples_polled[i]);
}
/* ADC interrupt mode example. */
QM_PUTS("\nADC interrupt mode");
/* Request the necessary IRQs. */
qm_ss_irq_request(QM_SS_IRQ_ADC_0_INT, qm_ss_adc_0_isr);
qm_ss_irq_request(QM_SS_IRQ_ADC_0_ERROR_INT, qm_ss_adc_0_error_isr);
/* Set up xfer. */
xfer.ch = channels;
xfer.ch_len = NUM_CHANNELS;
xfer.samples = samples_interrupt;
xfer.samples_len = NUM_SAMPLES_INTERRUPT;
xfer.callback = callback;
xfer.callback_data = NULL;
if (qm_ss_adc_irq_convert(QM_SS_ADC_0, &xfer)) {
QM_PUTS("Error: qm_adc_irq_convert failed");
return 1;
}
/* Wait for the callback. */
while (false == complete)
;
if (!callback_error) {
QM_PUTS("---COMPLETE CALLBACK---");
} else if (overflow_error) {
QM_PUTS("Error: ADC FIFO overflow");
return 1;
} else if (underflow_error) {
QM_PUTS("Error: ADC FIFO underflow");
return 1;
} else if (seq_error) {
QM_PUTS("Error: ADC sequencer error");
return 1;
}
/* Print the values of the samples. */
for (i = 0; i < NUM_SAMPLES_INTERRUPT; i++) {
QM_PRINTF("%d:%x ", i, (unsigned int)samples_interrupt[i]);
}
QM_PUTS("\nFinished: SS ADC");
return 0;
}
